TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 119

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Address
6.5. Register Map Convention
6.5.1. Addressing
TX4939 internal registers are to be accessed through 64 K bytes address space that is based on physical address
0xF_FF1F_0000 or pointed address by RAMP register. Figure 6-7 shows how to generate internal register address.
Physical address 1 and physical address 2 shown Figure 6-7 access the same register.
In TX49/H4 Core, the physical address from 0xF_FF00_0000 to 0xF_FF3F_FFFF are uncached mapped to the virtual
address from 0xFF00_0000 to 0xFF3F_FFFF (32 bit mode) /from 0xFFFF_FFFF_FF00_0000 to
0xFFFF_FFFF_FF3F_FFFF (64 bit mode).
This space includes the region from 0xF_FF1F_0000 allocated TX4939 internal registers at initialization.
6.5.2. Endianness and Register size
As this system has been designed based on the philosophy of Bi-Endian, all register address is defined as such that any
register less than 32 bits are accessed with 32 bit and 64 bit registers with 64 bit. However, it does not limit the 64 bit
register to be accessed with 32 bit.
As far as all 32 bit register and less than 32 bit register should be accessed only with 32 bit operation. Other type of access
may cause undefined result.
On the other hand, 64 bit registers can be accessed also with 32 bit operation. But the access address might change
depending on the system Endianness. Table 6-6 and Table 6-7 describes the access address of 32 bit portion in the 64 bit
register. Please note that access way is dependent on register.
Rev. 3.1 November 1, 2005
Base Address Register
(0xF_FF1F_0000)
Base Address
Table 6-6 32-bit Size Access to 64-bit Register (SRAM, EBUSC, PCIC1, PCIC, DMAC0/1)
0x*_****_***0
0x*_****_***8
0x*_****_***4
0x*_****_***C
(RAMP)
(######## indicates 32 bits data (upper 32 bits or lower 32 bits) which are accessed.)
(######## indicates 32 bits data (upper 32 bits or lower 32 bits) which are accessed.)
Table 6-7 32-bit Size Access to 64-bit Register (CRYPT, DDR, Config)
Address
Figure 6-7 Generating Physical Address for a Internal Register
0x*_****_***0
0x*_****_***8
0x*_****_***4
0x*_****_***C
Address
+
+
(Bit which are accessed)
[63….....32] [31….....0]
[63….....32] [31….....0]
########
Offset Address
Offset Address
Big Endian
6-9
########
(Bit which are accessed)
[63….....32] [31….....0]
[63….....32] [31….....0]
########
Big/Little Endian
=
=
########
(Bit which are accessed)
[63….....32] [31….....0]
[63….....32] [31….....0]
########
Little Endian
Physical Address 1
Physical Address 2
Toshiba RISC Processor
########
TX4939
6
6