TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 250

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

RTC
11.3.4.
The RTCADR address the RAM contents described in Table 11-3 Address Mapping of Exposed Registers. This register is
R/W.
Default: 8’hxx
11.3.5.
Any of exposed register can be accessed through this port with the value of RTCADR [7:0] register. After each read or write
operation, RTCADR [7:0] will increment one automatically. After 255 of RTCADR [7:0], it returns zero.
Default: 8’hxx
11.3.6.
Time Base Corrector register. This register is used to adjust the 48 bit time count value. Refer to 11.4 for more detail.
Rev. 3.1 November 1, 2005
RTCTBC
Field Definition
R/W
DEFAULT
RTCTBC
RTCTBC[7]
RTCTBC[6:0]
Address Register (RTCADR)
Data port to access the contents of RTC Register (RTCDAT)
Time Base Corrector Register (RTCTBC)
PM
R/W
0
Bit
1
7
7
0
Description
PM
Direction of Correction
PM = 1: Delay the time base with COMP[6:0] (unit PPM)
PM = 0: Advance the time base with COMP[6:0] (unit PPM)
COMP[6:0]
Compensation Value
COMP[6:0] can be 0 to 127 (unsigned integer)
If COMP[6:0] is set to non-zero value, then time base correction will happen.
Direction of Correction is defined by the value of PM bit.
6
0
5
11-6
0
4
0
COMP
R/W
3
0
2
Toshiba RISC Processor
0
1
0xFB04
0xFB08
0xFB0C
0
0
TX4939
11
11