TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 378

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.9. Post Write Function
The Post Write function improves system performance by completing the original bus Write transaction without waiting for
the other bus to complete its transaction when the first bus issues a Write transaction. Initiator Write can Post Write a
maximum of four (4) Write transactions, and Target Write can Post Write a maximum of five (5) Write transactions.
Due to compatibility issues with old PC software in the PCI specifications, performing Post Writes with Initiator Configuration
Write and Target I/O Write is not recognized. However, the TX4939 PCI Controller can even perform Post Writes to these
functions. In order to guarantee that these Writes are completed by the target device, please execute Reads to the device
that performed the Write, then either refer to the read value (so the TX49/H4 core can support non-blocking load) or execute
the SYNC instruction.
16.3.10. Endian Switching Function
The TX4939 supports both the Little Endian mode and the Big Endian mode. On the other hand, the PCI Bus is defined in
Little Endian logic only. Therefore, when the TX4939 is in the Big Endian mode, either the software or the hardware must
perform some kind of conversion when exchanging data with the PCI Bus.
The hardware provided in this Endian Switching is described in Figure 16-10 below. Those swapping are controlled by
EXFER bit and BSWAP bit in corresponding registers, such as G2PMnGBASE, G2PIOGBASE, P2GMnGBASE, and
P2GIOGBASE. The BSWAP is 36
these bits are set according to the CPU Endianness.
Endian switching during initiator access is specified by the Swap bit (BSWAP, EXFER) of the G-Bus Base Address Register
(G2PMnGBASE, G2PIOGBASE) of the access window for each initiator access (see Table 16-5).
Endian switching during target access is specified by the Swap bit (BSWAP, EXFER) of the G-Bus Base Address Register
(P2GMnGBASE, P2GIOGBASE) of the access window for each target access (see Table 16-8).
And when the PDMAC is used, the Swap bit (BSWAP, EXFER) of the PDMAC Control Register is specified accordingly to
above Swap bit setting.
In case of Little Endian, there is no issue. But in case of Big Endian, swapping will happen between G-Bus and PCI Bus.
These swapping, even it is commonly used, just support DMA data transfer. Because of this, any read or write operation to
PCI by CPU should have appropriate counter measure.
Commonly used counter measure are “swap the data before write” and “swap the data after read”. Those detail will be
found in any Bi-Endian coded PCI Peripheral driver.
Rev. 3.1 November 1, 2005
G2PMnGBASE.EXFER = 0
G2PIOGBASE.EXFER = 0
P2GMnGBASE.EXFER = 0
P2GIOGBASE.EXFER = 0
G2PMnGBASE.BSWAP = 1
G2PIOGBASE.BSWAP = 1
P2GMnGBASE. BSWAP = 1
P2GIOGBASE. BSWAP = 1
63
GBusAddr[2] = 1
Little Endian
G-BUS
AD[2] = 1
AD[2] = 1
31
31
byte
byte
Little Endian
32-bit Bus
byte
byte
PCI Bus
32
th
31
bit and the EXFER is 37
byte
byte
AD[2] = 0
AD[2] = 0
GBusAddr[2] = 0
byte
byte
G-BUS
Figure 16-10 Endian Switching.
0
0
0
16-14
G2PMnGBASE.EXFER = 1
G2PIOGBASE.EXFER = 1
P2GMnGBASE.EXFER = 1
P2GIOGBASE.EXFER = 1
th
G2PMnGBASE.BSWAP = 0
G2PIOGBASE.BSWAP = 0
P2GMnGBASE. BSWAP = 0
P2GIOGBASE. BSWAP = 0
bit of those registers. Also the power on default value of
63
GBusAddr[2] = 0
Big Endian
G-BUS
AD[2] = 1
AD[2] = 1
31
31
byte
byte
Little Endian
Toshiba RISC Processor
32-bit Bus
byte
byte
PCI Bus
32
31
AD[2] = 0
AD[2] = 0
byte
byte
GBusAddr[2] = 1
byte
byte
G-BUS
0
0
REV 1.01
TX4939
0
16
16