TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 446
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Company:
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
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Part Number:
TX4939XBG-400
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20 000
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PCIC
Rev. 3.1 November 1, 2005
Bit
6
5
4
3
2
1
0
Mnemonic
NCCMP
NTCMP
CFGERR
PCIERR
CHNERR
DATAERR
Field Name
Normal Chain
Completion
Normal Data
Transfer
Complete
Rsvd
Configuration
Error
PCI Fatal Error
G-Bus Chain Error G-Bus Chain Bus Error (Default: 0x0)
G-Bus Data Error
Description
Normal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in the Normal state.
0: Indicates that Chain transfer has not ended since this bit was previously
cleared.
Normal Data Transfer Complete (Default: 0x0)
1: Indicates that the data transfer specified by the PDMAC Register ended in
the Normal state.
0: Indicates that data transfer has not ended since this bit was previously
cleared.
Configuration Error (Default: 0x0)
1: Indicates that either the current setting of the control portion in the Control
Register and the Address/Count Register are not consistent with each other
or the PDMAC stipulation is not being obeyed. DMA transfer stops.
0: Indicates that the current setting of the control portion in the Control
Register can be tolerated.
PCI Fatal Error (Default: 0x0)
1: Indicates that an error was signaled on the PCI Bus during the Chain
process.
0: Indicates that no error has been signaled on the PCI Bus since this bit was
previously cleared.
1: Indicates that a G-Bus error occurrred during the Chain process. DMA
transfer stops.
0: Indicates that no G-Bus error has occurred during the Chain process since
this bit was cleared.
G-Bus Data Bus Error (Default: 0x0)
1: Indicates that a G-Bus error occurred during the data transfer process.
DMA transfer stops.
0: Indicates that no G-Bus error has occurred during the data transfer process
since this bit was cleared.
Table 16-75 Status Register
16-82
Toshiba RISC Processor
R/W
R/W1C
R/W1C
⎯
R/W1C
R/W1C
R/W1C
R/W1C
TX4939
16
16
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