TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 515

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.8.4. Frame transmission procedure
18.3.8.4.1. IEEE 802.3 transmission protocol
The MAC Transmission Block consists of three State Machines. The Main State Machine executes MAC layer protocol
and controls the other two State Machines (Gap State Machine and Back Off State Machine). The Gap State Machine
fetches the timing gap between packets, then counts them. The Back Off State Machine executes the Back Off or
Resend algorithms of the 802.3 CSMA/CD protocol.
18.3.8.4.2. Interpacket gap (IPG) timing
When in the half duplex mode, the Gap State Machine measures 96-bit time from the point when the Carrier Sense
signal is deasserted. This time becomes the interpacket gap. Gap State Machine splits the 96-bit time into 64-bit and 32-
bit time, then precisely controls the timing at which transmission starts. If there is traffic with the first 64-bit time, the Gap
State Machine resets the counter to 0, then starts counting from the beginning. If there is traffic during the remaining 32-
bit time, the count continues as is and signals that 96-bit time has elapsed.
When in the full duplex mode, Gap State Machine starts counting along with transmission completion, then signals
transmission completion after 96-bit time passes.
18.3.8.4.3. Collision process and back off
When the Main State Machine detects a collision, it starts up the counter of the Back Off State Machine, waits for the
Back Off time to elapse, then attempts to resend the packet that caused the collision. The Back Off time is a multiple of
512-bit time (including × 0). When a collision happens in the same packet, the Main State Machine advances the internal
Trial Count counter by 1 each time this happens. Then, it causes an 11-bit pseudorandom number generator to generate
random numbers and output a subset of it. Each time this is retried, the subset increases in size by 1 bit. In this way, the
following formula is invoked by the hardware.
r is the slot time count that the MAC must wait when a collision occurs. n is the number of retransmission attempts. For
example, after the first collision, n=1 and r is a random number between 0 and 1. In this case, the pseudorandom number
generator is 1-bit wide and generates either 0 or 1 as a random number. For the second and subsequent attempts, r is a
random number between 0 and 3. In other words, State Machine is n=2, so the pseudorandom number generator looks
at the lower 2 bits and generates random numbers between 0 and 3.
Rev. 3.1 November 1, 2005
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0 ≤ r < 2
k = min(n, 10)
To transmit a frame, the Transmission Enable bit (TxEn) of the Transmission Control Register must be set, and
the Transmission Halt Request bit (TxHalt) must be cleared. Furthermore, the Halt Transmission Immediately bit
(TxHalt) and the Halt Request bit (HaltReq) of the MAC Control Register must be cleared. Usually, the above
conditions (such as storing a valid frame descriptor address in the Transmission Frame Descriptor address) are
set after initializing the DMA Controller. In this way, MAC instructs the DMA engine to transmit a frame to MAC
Transmission FIFO. At this time, the DMA Transmission Controller controls transfers to the MAC Transmission
FIFO.
The MAC Transmission Block starts transmitting data in the FIFO. However, the first 64 Bytes are held in the
FIFO until the net is fetched. Then, the MAC Transmission Block requests the next data and continues to transmit
until the DMA Transmission Controller indicates the end of transmission data. The MAC Transmission Block
generates pad bytes when necessary, adds CRC to the end of a packet, then ends transmission. The MAC
Transmission Block will then set the Transmission Complete bit (Comp) of the Transmission Status Register to
signal that transmission has ended. Finally, depending on the Interrupt Enable Register settings, an interrupt may
occur.
Data transfer via the RMII Interface is driven by a 50MHz or 5.0 MHz RMII Reference Clock (ExRCLK).
The MAC Transmission Block must not start transmitting to the net until 8-byte data is stored in the MAC
Transmission FIFO. The first 8 bytes transmitted are the preamble and Start Frame Delimiter (SFD), so the
allowable DMA latency when starting transmission is 16-byte time. The DMA Transmission Block does not
transmit data to the MAC Transmission FIFO until either the entire packet is stored in the DMA Transmission
buffer or the byte count set in the Transmission Threshold Register is stored in the DMA Transmission buffer. If a
Transmission Underrun error is generated, you can avoid an underrun by increasing the setting of the
Transmission Threshold Register.
The MAC Transmission Block performs a parity check. If a Parity error is generated, the MAC Transmission Block
aborts transmission, then resets the FIFO and sets the Transmission Parity Error bit (TxPar) of the Transmission
Status Register.
k
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Toshiba RISC Processor
TX4939
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