TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 374

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.7. Initiator Access (G-Bus → PCI Bus Address Conversion)
During PCI initiator access, the G-Bus address of the Burst transaction issued by the G-Bus that was converted into the
PCI Bus address is used to issue a Burst transaction on the PCI Bus. 36-bit physical addresses (G-Bus addresses) are
used on the G-Bus. Also, 40-bit PCI Bus addresses are used on the PCI Bus.
Three memory access windows and one I/O access window can be set in the G-Bus space (Figure 16-6). The size of
each window is variable. When Burst transactions are issued to these access windows on the G-Bus, then that G-Bus
address is converted into a PCI Bus address that is used to issue a Burst transaction to the PCI Bus as the initiator. PCI
memory access is issued when the access window is the memory access window. PCI I/O access is issued when the
access window is the I/O access window. Dual access cycles are also issued to the PCI Bus when the PCI Bus address
exceeds 0x00_FFFF_FFFF.
When expressed as a formula, conversion of a G-Bus address (GBusAddr[35:0]) into a PCI Bus Address (PCIAddr[39:0])
is as follows below. GBASE[35:8], PBASE[39:8], and AM[35:8] each represent the setting register of the corresponding
access window indicated below in Table 16-4. The “&” symbol indicates a logical AND for each bit, “||” indicates a logical
OR for each bit, “!” indicates logical NOT, and “|” indicates bit linking.
Rev. 3.1 November 1, 2005
Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
0xFF_FFFF_FFFF
0x00_0000_0000
PCI IO Space
If (GBusAddr[35:8] & ! AM[35:8] == GBASE[35:8] & ! AM[35:8]) then
Table 16-4 Initiator Access Space Address Mapping Register
G-Bus Base Address
GBASE[35:8]
G2PM0GBASE.BA[35:8]
G2PM1GBASE.BA[35:8]
G2PM2GBASE.BA[35:8]
G2PIOGBASE.BA[35:8]
PCIAddr[39:0] =
Figure 16-6 Initiator Access Memory Window
Memory Access Window
Memory Access Window
Memory Access Window
IO Access Window
G-Bus Space
| ((PBASE[35:8] & ! AM[35:8]) || (GBusAddr[35:8] & AM[35:8]))
| GBusAddr[7:0];
0xF_FFFF_FFFF
0x0_0000_0000
PBASE[39:36]
16-10
PCI Bus Base Address
PBASE[39:8]
G2PM0PBASE.BA[39:8]
G2PM1PBASE.BA[39:8]
G2PM2PBASE.BA[39:8]
G2PIOPBASE.BA[39:8]
Address Mask
AM[35:8]
G2PM0MASK.AM[35:8]
G2PM1MASK.AM[35:8]
G2PM2MASK.AM[35:8]
G2PIOMASK.AM[35:8]
PCI Memory Space
0xFF_FFFF_FFFF
0x00_0000_0000
Toshiba RISC Processor
TX4939
16
16