TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 541

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Hardware resets initialize the DMA Control Register as follows:
0x20 of the lower byte denotes the default (32 Bytes = 8 double words) of the DMBurst field.
The DMA Control Register controls data transfer functions in the Master mode such as the Burst side, Big Endian
handling, and the test mode. This register also controls various DMA functions during transmission such as wake up and
software interrupts.
The DmBurst field controls the data transfer size with which the PCI Bus was used when operating in the Master mode.
Bits 8:0 set the data transfer size (DMA Burst size), but the lower 2 bits are fixed to “0” and must be a multiple of 4. After
a hardware reset, the default value becomes 32 Bytes, in other words 8 double words. You can change this value using a
software driver. You cannot set the DmBurst field to “0”. Writing of “0” to this field is ignored. Generally, a multiple of the
PCI cache line size is set in the DmBurst field. If the Burst size is 4, 8 or 12 when in the 100 Mbps full duplex mode, you
have to take into consideration throughput reduction of the PCI Bus.
The TestMode bit enables test functions such as those that enable reading or writing to all areas of the internal DMA
buffer or those that display internal status information in the reserved bits of a register.
The TxBigE bit and RxBigE bit enable the transmitting or receiving of data with Big Endian mode devices. However, it is
important to note that only the data (bytes in the area designated by the buffer descriptor) is handled in the Big Endian
mode. Control information such as frame descriptors and buffer descriptors are always in a format unique to the PCI Bus.
In other words, they are in the Little Endian format.
The TxWakeUp bit enables immediate data transmission without waiting for the end of the current polling cycle. Setting
the TxWakeUp bit to “1” while the transmitter is polling aborts the current polling cycle. When the current polling cycle
ends, the current TxWakeUp bit is cleared. Any writing of “0” to the TxWakeUp bit is ignored.
Software interrupts are made available to support software drivers.
The IntMask bit disables all interrupt sources. Therefore, even when the processing of interrupt sources is in progress,
the software driver can put interrupts in the Enable state again.
The M66EnStat bit is used to control the MAC clock divide circuit when driving serial addresses of the MII station
manager.
Rev. 3.1 November 1, 2005
0000_1020h:
0008_1020h:
When the PCI Bus speed is 0-33 MHz
When the PCI Bus speed is 33-66 MHz
18-49
Toshiba RISC Processor
TX4939
18
18