TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 353

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
DDR_CTL_15 = 0x8078
DDR_CTL_16 = 0x8080
DDR_CTL_17 = 0x8088
Rev. 3.1 November 1, 2005
Name
DRIVE_DQ_DQS
-
AP
-
Name
CS_MAP
-
POWER_DOWN
-
Name
TXSR
SREFRESH
-
Bits
0:0
7:1
8:8
15:9
Bits
1:0
7:2
8:8
15:9
Bits
7:0
8:8
15:9
Default
0x0
-
0x0
-
Default
0x0
-
0x0
-
Default
0x00
0x0
-
Range
0x0-0x1
-
0x0-0x1
-
Range
0x0-0x3
-
0x0-0x1
-
Range
0x0-0xff
0x0-0x1
-
15-23
Description
Enable feature to keep output enables on dq and dqs drives active
when controller is idle.
This parameter selects if the dq and dqs output enables will driven
active when the controller is in an idle state.
0 - Leave the output enables in High-Z when idle
1 - Drive the output enables active when idle.
Reserved
Enable autorefresh mode of controller.
Enable Auto Precharge mode for DRAM devices.
0 = Auto precharge mode disabled. All read and write transactions
are issued such that the banks stay open until another request needs
the bank or the max open time (tras_max) has expired or a refresh
command closes all banks.
1 = Auto precharge mode enabled. All read and write transactions
are terminated by an auto precharge command. If a transaction
consists of multiple read or write commands, only the last command
is issued with an auto precharge.
Reserved
Description
Number if active chip selects used in address decoding.
This register is programmed with a mask that determines which chip
select pins are active. The user address CS field will be mapped
into the active chip selects indicated by this register in ascending
order from lowest to highest.
This allows the controller to map the entire contiguous user address
into any group of chip selects. Bit 0 of this register corresponds to
chip select[0].
Reserved
Place DRAMs in power down state.
When this register is written with a “1”, the controller will disable the
clock enable pin to the DRAM devices as soon as the current burst
for the current transaction, if any, the controller is processing, has
completed. Any subsequent commands in the command queue will
be suspended until this register is written with a “0”. The controller
will continue to issue refresh commands and any precharge
commands necessary on open banks while in power down mode.
This means that the DRAM will automatically be brought out of
power down mode for these operations.
Reserved
Description
DRAM TXSR parameter in cycles.
Self refresh exit time in cycles
Place DRAMs in self-refresh mode.
When this register is written with a “1”, the DRAM device(s) will be
placed in self-refresh mode. In order to put the DRAMs in self refresh
mode, the current burst for the current transaction, if any, will
complete, all banks will be closed, the self refresh command will be
issued to the DRAM, and the clock enable pin will be de-asserted.
The system will remain in self-refresh mode until this register is
written with a “0”. The DRAM devices will return to normal
operating mode after the self-refresh exit time (txsr) of the device
and any dll initialization time for the DRAM is reached. The
controller will resume processing of commands where it was
interrupted if it were processing a transaction when the register was
written.
Reserved
2'b01 = chip select[0] is enabled
2'b10 = chip select[1] is enabled
2'b11 = Both chip select[0] and chip select[1] are enabled
Toshiba RISC Processor
TX4939
15
15

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