TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 21
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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Index
Rev. 3.1 November 1, 2005
Figure 18-30 PCI Interrupt Register.................................................................................................................... 18-45
Figure 18-31 Power Management Function Register ......................................................................................... 18-46
Figure 18-32 Power Management Control, Status Register ............................................................................... 18-46
Figure 18-33 DMA Control Register.................................................................................................................... 18-48
Figure 18-34 Transmission Frame Pointer Register ........................................................................................... 18-50
Figure 18-35 Transmission Threshold Register .................................................................................................. 18-51
Figure 18-36 Transmission Polling Control Register........................................................................................... 18-52
Figure 18-37 Buffer List Frame Pointer............................................................................................................... 18-53
Figure 18-38 Reception Fragment Size Register................................................................................................ 18-54
Figure 18-39 Interrupt Enable Register .............................................................................................................. 18-55
Figure 18-40 Free Descriptor Area Base Register.............................................................................................. 18-56
Figure 18-41 Free Descriptor Area Size Register ............................................................................................... 18-56
Figure 18-42 Interrupt Source Register .............................................................................................................. 18-57
Figure 18-43 Pause Count Register ................................................................................................................... 18-59
Figure 18-44 Remote Pause Count Register...................................................................................................... 18-59
Figure 18-45 Transmission Control Frame Status Register ................................................................................ 18-60
Figure 18-46 MAC Control Register ................................................................................................................... 18-61
Figure 18-47 ARC Control Register .................................................................................................................... 18-62
Figure 18-48 Transmission Control Register ...................................................................................................... 18-63
Figure 18-49 Transmission Status Register (2/2)................................................................................................ 18-64
Figure 18-50 Reception Control Register ........................................................................................................... 18-65
Figure 18-51 Reception Status Register ............................................................................................................. 18-67
Figure 18-52 Station Management Data Register............................................................................................... 18-69
Figure 18-53 Station Management Control Address Register............................................................................. 18-70
Figure 18-54 ARC Address Register................................................................................................................... 18-71
Figure 18-55 ARC Data Register ........................................................................................................................ 18-72
Figure 18-56 ARC Enable Register .................................................................................................................... 18-73
Figure 18-57 Missed Error Count Register ......................................................................................................... 18-74
Figure 19-1 SIO Internal Block Diagram ............................................................................................................... 19-2
Figure 19-2 Data Frame Configuration ................................................................................................................. 19-4
Figure 19-3 Baud Rate Generator and SIOCLK Generator ................................................................................... 19-5
Figure 19-4 Relationship Between Interrupt Status Bits and Interrupt Signals.................................................... 19-10
Figure 19-5 Example Configuration of Multi-Controller System ...........................................................................19-11
Figure 19-6 Line Control Register....................................................................................................................... 19-13
Figure 19-7 DMA/Interrupt Control Register ........................................................................................................ 19-15
Figure 19-8 DMA/Interrupt Status Register.......................................................................................................... 19-17
Figure 19-9 Status Change Interrupt Status Register ......................................................................................... 19-19
Figure 19-10 FIFO Control Register ................................................................................................................... 19-20
Figure 19-11 Flow Control Register .................................................................................................................... 19-21
Figure 19-12 Baud Rate Control Register ........................................................................................................... 19-23
Figure 19-13 Transmit FIFO Register .................................................................................................................. 19-24
Figure 19-14 Receive FIFO Register................................................................................................................... 19-25
Figure 20-1 SPI Block Diagram ............................................................................................................................. 20-2
Figure 20-2 Transfer Format when SPHA is “0”..................................................................................................... 20-5
Figure 20-3 Transfer Format when SPHA is “1”..................................................................................................... 20-6
Figure 20-4 SPI Master Control Register (SPMCR) .............................................................................................. 20-9
Figure 20-5 SPI Control Register 0 (SPCR0) ...................................................................................................... 20-10
Figure 20-6 SPI Control Register 1 (SPCR1) .......................................................................................................20-11
Figure 20-7 SPI Interframe Delay Time Counter (SPFS)..................................................................................... 20-12
Figure 20-8 SPI Status Register (SPSR) ............................................................................................................. 20-13
Figure 20-9 SPI Data Register (SPDR) ............................................................................................................... 20-14
Figure 21-1 CIR Block Diagram............................................................................................................................. 21-2
Figure 21-2 Pulse-Coded Signal............................................................................................................................ 21-3
Figure 21-3 Space-Coded Signal........................................................................................................................... 21-3
Figure 21-4 CIR Control/Status Register ............................................................................................................... 21-4
Figure 22-1 Block Diagram of I2C Controller ......................................................................................................... 22-1
Figure 22-2 I2C Protocol ....................................................................................................................................... 22-7
Figure 22-3 Clock Synchronization........................................................................................................................ 22-8
Figure 22-4 Internal structure I2C.......................................................................................................................... 22-9
Figure 22-5 Control Flow ......................................................................................................................................22-11
Figure 22-6 Bit Command Control ....................................................................................................................... 22-12
Figure 22-7 Byte Mode ........................................................................................................................................ 22-13
Figure 22-8 Byte Mode ........................................................................................................................................ 22-14
Figure 23-1 the block diagram of the I2SC Interface module. ............................................................................... 23-1
Figure 23-2 the block diagram for I2S clock diagram. ........................................................................................... 23-2
Figure 23-3 I
2
S Interface........................................................................................................................................ 23-3
xvii
Toshiba RISC Processor
TX4939
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