TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 575

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
SIO
The Reception Error Interrupt bit (SIDISR.ERI) of the DMA/Interrupt Status Register (SIDISRn) is set when one of the
following errors is detected: an overrun error, a parity error, or a framing error. An interrupt is signaled if the Reception Error
Interrupt Enable bit of the DMA/Interrupt Control Register (SIDICRn) is set.
The UART Break Detect bit (UBRKD) and the Receiving Break bit (RBRKD) of the Status Change Interrupt Status Register
(SISCISR) is set when a break is detected. The UART Break Detect bit (UBRKD) remains set until it is cleared by the
software. The Receiving Break bit (RBRKD) is automatically cleared when a frame is received that is not a break.
The status of the next reception data to be read is set to the Overrun Error bit (UOER), Parity Error bit (UPER), Framing Error
bit (UFER), and the Receive Break bit (RBRKD). Each of these statuses is updated when reception data is read from the
Receive FIFO Register (SIRFIFOn).
During DMA transfer, an error is signaled and DMA transfer stops with error data remaining in the Receive FIFO if either an
error (Framing Error, Parity Error, or Overrun Error) or a Reception time out (TOUT) is detected. If a Reception Error occurs
during DMA transfer, use the Receive FIFO Reset bit (RFRST) of the FIFO Control Register (SIFCRn) to clear the Receive
FIFO. However, a software reset will be required if a reception overrun error has occurred. Refer to “19.3.10 Software Reset”
for more information.
19.3.9. Reception Time Out
A Reception time out is detected and the Reception Time Out bit (TOUT) of the DMA/Interrupt Status Register (SIDISR) is
set under the following conditions.
19.3.10. Software Reset
It is necessary to reset the FIFO and perform a software reset in the following situations.
Software reset is performed by setting the Software Reset bit (SWRST) of the FIFO Control Register (SIFCR). This bit
automatically returns to “0” after initialization is complete. This bit must be set again since all SIO registers are initialized by
software resets.
Rev. 3.1 November 1, 2005
this occurs, 2 frames (2 Bytes) of 0x00 data are stored in the Receive FIFO.
Non-DMA transfer mode (SIDICRn.RDE = 0):
When at least 1 Byte of reception data exists in the Receive FIFO and the data reception time for the 2 frames (2
Bytes) after the last reception has elapsed
DMA transfer mode (SIDICRn.RDE = 1):
When the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed regardless of whether
reception data exists in the Receive FIFO
After transmission data is set in FIFO, etc., transmission started but stopped before its completion
An overrun occurred during data reception
19-9
Toshiba RISC Processor
TX4939
19
19

Related parts for TX4939XBG-400