TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 523

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.9. DMA operation
This subsection describes the programming of the PCI-mounted Ethernet Controller. The programming details differ
slightly depending on whether you select batch processing as the control mode or select Continuous Polling. Unless
otherwise stated, the descriptions in this subsection assume the use of Continuous Polling.
Following is the structure of this subsection.
18.3.9.1. Initial setup of PCI
When initially setting up the system, you can use the IDSel signal to write to the PCI Configuration Register. This makes
it possible for the system to map the Ethernet Controller to a memory boot address space then transfer data to the boot
address space to output the IDSel signal.
Registers such as the following require initial setup.
Rev. 3.1 November 1, 2005
Note:
Initial setup of PCI
Initial setup of DMA and MAC
Initializing the queues
Transmitting frames
Receiving frames
Handling interrupts
PCI I/O Base Address Register or PCI Memory Base Address Register: To map the register to an I/O address
space or memory space
PCI Command Register: To customize the PCI function
There are also situations where the following register requires initial setup.
PCI Interrupt Register: To customize latency or signal interrupt factors to external pins
If you use the SRAM in the DMA Controller without initializing it, Packet errors may be mistakenly detected
during packet reception. Implement the following initialization procedure to prevent this phenomenon
from occurring.
(1)
(2)
(3)
Prepare for initial setup
Set (write "1" to) the TestMode bit (bit 13) of the DMA_Ctl (0x00) Register.
Initialize on-chip memory
Implement the following on all addresses (0x000-0x3FF) of the on-chip SRAM.
Cancel the Test mode
Reset (write "0" to) 1 in the TestMode bit (bit 13) of the DMA_Ctl (0x00) Register.
(i) Set the on-chip SRAM address in ARC_Adr (0x60). (ARC_Loc field: 0x000-0x3FF)
(ii) Write initialization data 0x0000_0000 to ARC_Data (0x064). (32-bit write)
You can implement the following to confirm the written data.
Read ARC_Data(0x64). (32-bit read)
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Toshiba RISC Processor
TX4939
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