TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 238

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.5.2. NAND Flash Memory Mode Control Register (NDFMCR) 0x5008
Rev. 3.1 November 1, 2005
Bits
31 : 11
10
9:8
7
6 : 5
4
3 : 2
1
0
15
14
NDFMCR
RESERVED
Mnemonic
–
X16
DMAREQ
WE
ECC
CE
CS [1:0]
ALE
CLE
13
12
Figure 10-10 NAND Flash Memory Mode Control Register (NDFMCR)
Table 10-5 NAND Flash Memory Mode Control Register (NDFMCR)
Field Name
Reserved
X16BUS
DMA Request
Write Enable
ECC Control
Chip Enable
Chip Select
Address Latch
Enable
Command Latch
Enable
11
R/W
X16
10
0
R/W
DMAREQ
9
0
Description
–
Indicate NAND Flash has 16-bit Bus. (Default: 0)
0: 8-bit Bus (Default)
1: 16-bit Bus.
Initiate DMA data transfer (Default: 00)
Invoke DMA transfer from/to NDFDTR port to memory in system.
00: No DMA
01: 128 Byte Transfer
10: 256 Byte Transfer
11: 512 Byte Transfer
These bits will be cleared when all the requested bytes have been transferred from
NAND Flash to FIFO
Write Enable (Default: 0)
When CPU references NDFDTR register, it generates external bus READ operation
with non-conditional ND_LA and ND_RE* assertion.
When CPU writes a value to NDFDTR register, it also generates external bus
WRITE operation with ND_LA and conditional ND_WE* assertion.
During Command and Address write cycle with either ALE or CLE assertion,
ND_WE* signal assert non-conditional.
In other cases, both ALE and CLE = 0, ND_WE* signal assertion is controlled by this
bit as follows.
ECC Control (Default: 00)
This field specifies the operation of the ECC calculation circuit.
11: Reset the ECC circuit.
00: Disable the ECC circuit.
01: Enable the ECC circuit.
10: Read the ECC circuit the NDFMC calculated.
Chip Enable Default: 0)
Enables access to NAND flash memory. Set this bit when accessing NAND flash
memory.
0: Disable (ND_CE* high.)
1: Enable (ND_CE* low.)
Chip Select
Address Latch Enable (Default: 0)
Specifies the ND_ALE* signal.
0: Low
1: High
Command Latch Enable (Default: 0)
Specifies the value of the NC_CLE signal.
0: Low
1: High
Note
0: Disable ND_WE* assertion (See Note below)
1: Enable ND_WE* assertion
R/W
8
0
Write operation to NDFDTR with WE=0, ALE=0, CLE=0, can be used to
synchronize external latch with the contents of NDFMCR register.
10-14
R/W
WE
7
0
R/W
6
0
ECC
R/W
5
0
R/W
CE
4
0
R/W
3
0
CS[1:0]
Toshiba RISC Processor
R/W
2
0
R/W
ALE
1
0
CLE
R/W
0
0
TX4939
: Default
: Type
10
10