TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 196

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.7.1.
When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the ACK*/Ready Dynamic mode. The
ACK*/Ready signal becomes High-Z when it is in the ACK*/Ready Static mode.
Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access cycle. The Wait cycle count
is 0 to 0x3e (becomes the external ACK mode when set to EBCCRn.PWT: WT = 0x3f).
9.2.7.2.
When in this mode, the ACK*/READY pin becomes ACK* input, and the cycle is ended by the ACK* signal from an external
device. ACK* input is internally synchronized. Refer to Section "7.3.7.4 ACK* Input Timing" for more information regarding
timing.
Rev. 3.1 November 1, 2005
ACK*/READY
ACK*/READY
SWE*/BWE*
SWE*/BWE*
SADB [15:0]
SADB [15:0]
AD [28:6]
AD [28:6]
SYSCLK
SYSCLK
SA [5:0]
SA [5:0]
output
ACE*
ACE*
input
Normal Mode
External ACK Mode
OE*
OE*
CE*
CE*
0
0
1
1
EBCCRn.PWT:WT=3
0
2
2
1
3
3
Figure 9-3 External ACK Mode (ACEHOLD=0)
4
2
4
Figure 9-2 Normal Mode (ACEHOLD=0)
External ACK Mode (ACEHOLD=0)
3
5
5
Normal Mode (ACEHOLD=0)
EBCCRn.SHWT=0
6
6
7
7
9-6
8
8
9
9
10
10
11
11
12
12
13
13
14
14
Toshiba RISC Processor
15
15
16
16
17
17
18
18
19
19
TX4939
Rev 2.13
Rev 2.13
9
9