TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 616

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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I2C
22.2.5. I2C Control Register (I2C_CTR)
Rev. 3.1 November 1, 2005
Bit
31:17
16
15:12
11
10
9
8
7:3
2
1
0
Reset Value
Reset Value
R/W/RO
R/W/RO
Bit
Bit
RO
RO
31
15
0
0
Field Name
Reserved
I2Creset
Reserved
GIOSDAi
GIOSCLi
GIOSDAC
GIOSCLC
Reserved
GPIO enable
I2C Mode
Select
I2C enable
RO
RO
30
14
0
0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Description
I2C Reset.
SDA signal status
This bit shows the status of SDA signal (H or L)
SCL signal status
This bit shows the status of SCL signal (H or L)
SDA control
Only valid when GPIO enable bit is set
SCL control
Only valid when GPIO enable bit is set
GPIO Mode Enable
If this bit is set, I2C controller will be disable.
I2C Mode Select
Firmware must not write “1” to this bit.
I2C Mode Enable
If this bit is set, I2C controller will be enable.
RO
RO
27
11
0
?
0: normal (default)
1: Reset all pointers and all internal state machine.
0: drive SDA = “0”
1: release SDA
0: drive SCL = “0”
1: release SCL
0: Disabled (default)
1: Enabled GPIO Mode
0: Byte Mode (defaut)
1: Reserved
0: Disable I2C logic
1: Enabled I2C Mode
RO
RO R/W R/W RO
26
10
0
?
22-6
RO
25
0
9
1
RO
24
0
8
1
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
5
0
0
RO
RO
20
0
4
0
Toshiba RISC Processor
RO
RO R/W R/W R/W
19
3
0
0
RO
18
0
2
0
0xF920
RO R/W
17
1
0
0
16
0
0
0
TX4939
22
22

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