TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 554

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.5.2. ARC Control Register
Hardware resets initialize the ARC Control Register to 0x0000. Software resets do not change the register contents.
The ARC recognizes the three following Ethernet address types.
When the CompEn bit is set and the ARC’s Compare mode is validated, the recipient address of the reception packet is
compared with the address stored in ARC memory. For information on the structure of ARC memory, see 18.3.8.6
Address Recognition Circuit (ARC) operation.
When the CompEn bit is cleared, the ARC unconditionally halts address comparisons. When an Accept bit (StationAcc,
GroupAcc, or BroadAcc) is set, packets the ARC refused are also accepted. To refuse all packets, clear all bits of the
ARC Control Register. To put MAC in the Promiscuous mode and accept all normal packets, set the ARC to accept all
three of the above address types. You can also put MAC in the Promiscuous mode by setting the Negative ARC bit and
clearing the CompEn bit.
When the ARC Compare mode is enabled, addresses for filtering reception messages are read from ARC memory. ARC
memory has a 6-Byte structure for each entry.
You can set it to Valid or Invalid for each entry as described in ARC Enable Register on page 86.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 5
4
3
2
1
0
Default
Default
Name
Name
TYPE
TYPE
Station addresses: The first byte is even such as in 00-00-00-00-00-00.
Broadcast addresses: Defined as FF-FF-FF-FF-FF-FF.
Multicast group address: The first byte is odd such as in 01-00-00-00-00-00.
However, not FF-FF-FF-FF-FF-FF.
Mnemonic
CompEn
NegARC
BroadAcc
GroupAcc
StationAcc
31
15
30
14
Field Name
Reserved
Compare Enable
Negative ARC
Broadcast Accept
Group Accept
Station Accept
29
13
28
12
27
11
Figure 18-47 ARC Control Register
Reserved
0x44
26
10
Description
CompEn (Default: 0, R/W)
Enables the Compare mode.
NegARC (Default: 0, R/W)
0: Accepts packets the ARC recognized, but refuses all other packets.
1: Refuses packets the ARC recognized, but accepts all other packets.
BroadAcc (Default: 0, R/W)
Accepts all packets that have a broadcast address.
GroupAcc (Default: 0, R/W)
Accepts all packets that have a multicast group address.
StationAcc (Default: 0, R/W)
Accepts all packets that have a unicast station address.
25
9
18-62
RESERVED
24
8
23
7
22
6
21
5
CompEn NegARC BroadAcc GroupAcc StationAcc
R/W
20
4
0
Toshiba RISC Processor
R/W
19
3
0
R/W
18
2
0
R/W
17
1
0
TX4939
R/W
16
0
0
18
18