TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 597

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.3.4. Transfer format
During SPI transfer, serial data transmission (shift out) and reception (shift in) is executed simultaneously. At this time, serial
data is shifted or sampled synchronous to the serial clock.
The SPHA bit and SPOL bit of SPI Control Register 0 (SPCR0) determine the transfer format. The setting of the SPHA bit
broadly classifies the protocol that is used. Each protocol is described below in items 20.3.4.1 and 0.
20.3.4.1. SPHA = 0 format
Figure 20-2 shows the transfer format when SPHA is “0”.
When in this format, data is sequentially fetched from the first clock edge after the Idle state. When the SPOL bit is “0”, data
is fetched at the rising edge. When this bit is “1”, data is fetched at the falling edge. The SPIIN or SPIOUT signal is switched
at the second clock edge of SPICLK. The signal is switched at the SPICLK falling edge when the SPOL bit is “0”, or is
switched at the SPICLK rising edge when the SPOL bit is “1”. When the SPOL bit is “0”, SPICLK is at the Low level during
the Idle state. When the SPOL bit is “1”, SPICLK is at the High level during the Idle state.
Rev. 3.1 November 1, 2005
SPICLK
(SPOL=0)
SPICLK
(SPOL=1)
SPIIN
SPIOUT
idle
MSB
MSB
1
Sample point
2
B6
B6
Figure 20-2 Transfer Format when SPHA is “0”
B5
B5
3
20-5
4
B4
B4
B3
B3
5
6
B2
B2
Toshiba RISC Processor
B1
B1
7
LSB
LSB
8
TX4939
idle
20
20