TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 489

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.5.6. Command Packet Transmission Timing
GBUSCLK
AB
CSN
BEN[0]
BEN[1]
LASTN
ACKN
ACKN_E
The above figure is a timing chart that shows the situation when using the ATAPI Packet Command Register described in
Section 17.3.3.19 to issue a command packet to the device. Ultra DMA is used as the transfer protocol. Also, Ultra DMA
uses the mode selected by bits [7:4] of the System Control Register described in Section 17.3.2.4.
Command packets usually consist of 12 bytes, and these 12 bytes accumulate in the FIFO in the Controller when 6
consecutive accesses to the ATAPI Packet Command Register are performed. The command packet is sent to the device
after accumulated in the FIFO in the controller.
In addition to the timing shown here, you can transmit data using the same timing as register transfer using the setting of bit
[12](Packet Transfer Mode) of the Packet Transfer Control Register. Specifically, you can perform this transfer by using the
following setup routine to execute the transfer process.
Rev. 3.1 November 1, 2005
WRN
DB_IN
ATA_CLK
ATD_OUT
DMARQ
DMACKN
DIOWN
DIORN
IORDY
Execute transfer using data transfer
•
•
Packet Transfer Control Register
Packet Transfer Control Register
(Continuous write in the order
Write command to the ATAPI
Set the Packet Start bit of the
Specify transfer mode
Specify transfer word count
mode such as Ultra DMA
Command Register
transferred)
17-35
Toshiba RISC Processor
TX4939
17
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