TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 506

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
The reception circuit in the Flow Control Block recognizes the MAC control frame, and then performs the following Pause
operation. First, the Data Length/Data Type field must have a specific value for a MAC control frame. Second, the ARC
must recognize the destination address. Third, the frame length must by 64 Bytes including CRC. Fourth, the CRC test
result must confirm the correctness of the frame. Finally, the frame must include a valid Pause operation code and
operand.
If the Data Length/Data Type field does not contain a specific value that expresses a MAC control frame, MAC performs
no operation and the packet is treated as a typical packet. If the ARC cannot recognize the destination address, MAC
ignores the packet. If the packet length including CRC is not 64 Bytes, MAC does not perform Pause operation. In this
case, if Pass Through is in the Enabled state, the driver is handed off.
If the Control bit of the Transmission Status Register is set, you can detect full duplex mode Pause operation or other
MAC control function frames even if the transmitter itself is in the Pause state.
The Flow Control Block has two timers for Pause operation and a Control/Status Register for each timer. One timer,
register pair is used when the received packet pauses the transmitter. The other timer, register pair is used to estimate
the pause status of the transmission destination after the transmitter transmits a Pause command. The Command/Status
Register Interface is used to access the Transmission Control Register, the Transmission Status Register, the Reception
Control Register, and the Reception Status Register. You can use these registers to start transmission of a MAC Control
frame, enable or disable the MAC control function, or access the Flow Control counter.
You can use the Control bit to select whether to completely handle MAC Control frames inside the Ethernet Controller or
hand them off to the software driver. Therefore, default flow control is possible even if the software driver itself does not
support flow control.
18.3.6.4. MAC Control Register, Status Registers
MAC has a group of Control Registers and Status Registers. These registers are used to control the Transmission Block
or Reception Block, display MAC status, are used in the communication interface with CAM, and are used in the interface
with the MII Station Manager. These registers can also access from PCI using the memory map or I/O map. For details
on the MAC Control Register or Status Register, see 18.4.5 MAC Control, Status Register group.
18.3.6.5. MII Station manager
MAC in the Ethernet Controller handles station management data signals (MDIO and MDC) from the MII Controller, but it
does not interpret them. Using a serial interface defined by MII, the MII Station Manager reads and writes to/from the
Control Registers and Status Registers in a PHY device whose configuration is set up.
When it is necessary to access these registers to negotiate configuration using an application specialized for a bridge,
router, switching hub, etc., you can use the MAC Control Registers and Status Registers to trigger reads and writes
through the Station Management Data Interface. For details, see 18.4.5.5 Station Management Registers..
18.3.6.6. Reception packet alignment
When storing Reception packets in the buffer, the Ethernet Controller can skip by the set byte count. By default, the
Ethernet Controller does not skip Reception packets and these packets are on double-word boundaries. You can set the
DMA Control Register to have the first buffer skip 1-3 Bytes. This function is convenient when aligning packets when
internally necessary by handling IPs and decoding.
Rev. 3.1 November 1, 2005
18-14
Toshiba RISC Processor
TX4939
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