TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 366

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.1.4. PCI Arbiter
16.1.5. PDMAC (PCI DMA Controller)
16.1.6. Miscellaneous
Rev. 3.1 November 1, 2005
Supports six (6) external PCI bus masters
Uses the Programmable Fairness algorithm (two levels with different priorities for six (6) external and one internal
round-robin request/grant pairs)
Supports bus parking
Bus master uses the Most Recently Used algorithm
Unused slots and broken masters can be automatically disabled after Power On reset
On-chip arbitration function can be disabled and external arbiter can be used.
Direct Memory Access (DMA) Controller dedicated to 1-channel PCI
Is possible to transfer data using minimal G-Bus bandwidth
Data can be transferred bidirectionally between the G-Bus and the PCI Bus
Specifying a physical address on the PCI Bus and an address on the G-Bus makes it possible to automatically
transfer data between the PCI Bus and the G-Bus
Supports the Chain DMA mode, in which a Descriptor containing chain-shaped addresses and a transfer size is
automatically read from memory while DMA transfer continuous
On-chip 4-stage 64-bit data buffer
PCI BOOT
Boot from PCI Memory Space (0xFFFE_0000)
Satellite Mode
External Host is able to configure the TX4939 based Adapter System
External PCI Clock acceptable
16-2
Toshiba RISC Processor
TX4939
16
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