TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 81

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.3.10. Ethernet MAC Interface (RMII)
3.3.11. AC-Link Interface
3.3.12. I2S Interface 2-channel mode
Rev. 3.1 November 1, 2005
Ethernet MAC Channel 0 Interface
Signal Name
E0RCLKI
E0CRS_DV
E0RXD[1:0]
E0TX_EN
E0TXD[1:0]
E0RX_ER
E0MDC
E0MDIO
Ethernet MAC Channel 1 Interface
Signal Name
E1RCLKI
E1CRS_DV
E1RXD[1:0]
E1TX_EN
E1TXD[1:0]
E1RX_ER
E1MDC
E1MDIO
I2S Interface
Signal Name
I2S_WS0
I2S_SCK0
I2S_SD0
I2S_WS1
I2S_SCK1
I2S_SD1
AC-Link Interface
Signal Name
ACRESET*
BITCLK
SDIN[0]
SDOUT
SYNC
SDIN[1]
I/O
Output
Input
Input
PD
Output
Output
Input
PD
I/O
I/O
I/O
I/O
PD
I/O
I/O
I/O
PD
I/O
Input
Input
Input
Output
Output
Input
Output
I/O
I/O
Input
Input
Input
Output
Output
Input
Output
I/O
Function
AC'97 Master Hardware Reset
This is the AC’97 Master Hardware reset signal.
12.288 MHz Serial Data Clock
The BITCLK signal is an input clock from an external AC’97 device.
Serial, Time Division Multiplexed, AC'97 Input Stream
This is the serial Time Division Multiplexed AC’97 output stream input.
Serial, Time Division Multiplexed, AC'97 Output Stream
This is the serial Time Division Multiplexed AC’97 output stream output.
48 kHz Fixed Rate Sample Synchronous
This is 48kHz Fixed sample synchronous signal.
Serial, Time Division Multiplexed, AC'97 Input Stream
This is the serial Time Division Multiplexed AC’97 output stream input.
Function
Channel 0 Word Select
Channel 0 Bit Clock
Channel 0 Data
Channel 1 Word Select
Channel 1 Bit Clock
Channel 1 Data
Function
Reference Clock Input
Carrier Sense/Receive Data Valid from PHY
Receive Data
Transmit Enable
Transmit Data
Receive Error
Management data clock output
Management data bi-directional signal
Function
Reference Clock Input
Carrier Sense/Receive Data Valid from PHY
Receive Data
Transmit Enable
Transmit Data
Receive Error
Management data clock output
Management data bi-directional signal
3-9
Toshiba RISC Processor
TX4939
3
3