TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 91
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Boot Configuration
4.1. Boot Configuration
In boot time, following major things will be configured by external signal conditions.
The SA [5:0], DMAACK [2:0], and SADB [15:0] signals (External bus signals) can also function as configuration signals for
initially setting various functions upon booting the system. The states of the configuration signals immediately after the
RESET* is de-asserted are read as initial values for the TX4939 internal registers.
A High signal level sets a value of 1 and a Low signal level sets a value of 0.
All configuration signals are provided with internal pull-up resistors. To drive a signal Low, pull down the corresponding pin
on the board using an approx. 4.7 kΩ resistor. Driving a signal high does not require a pull-down resistor.
Any signals defined Reserved should not be pulled down.
Figure 4-1 shows Boot Configuration Timing
Table 4-1 describes each configuration signal.
Rev. 3.1 November 1, 2005
MSTCLK, MSTCLK2
All PLL Powers
DMAACK[2:0]
VddIN, VddIO
SADB[15:0]
PCI Controller Mode
□ Host Mode
□ Satellite Mode
Boot Device
□ NOR device on channel 0
□ ROM Device on PCI Bus (PCI Boot)
CPU Clock Configuration
□ CPU Pipeline Clock
□ GBUS Clock Frequency
□ SYSCLK Frequency
□ NOR device timing set (NOR Boot)
□ PCI Bus Clock Frequency
PC Trace Enable or not
ETC.
SA[5:0]
RESET*
Figure 4-1 Boot Configuration Settling Timing
MSTCLK, MSTCLK2 Stabilized Time
Boot Configuration Settling Timing Diagram
Boot Configuration Inputs Stabilized Time
All PLL Stabilized Time + Synchronous Reset Propagation Time
T
RESETW
Chapter 4. Boot Configuration
4-1
Toshiba RISC Processor
TX4939
4
4
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