TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 84

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.3.21. TEST and EJTAG Debugging Interface
Rev. 3.1 November 1, 2005
Signal Name
TEST Signals
TEST [0]*
BYPASSPLL*
div_RST*
JTAG and EJTAG signals
TRST*
EJRST*
TCK
TMS
TDI/(DINT*)
TDO/(TPC[0])
Additional Signals for PC Trace Function
DINT*
TPC[3:1]
DCLK
PCST [8:0]
I/O
Input
PU
Input
PU
Input
PU
Input
PD
Input
PD
Input
PU
Input
PU
Input
PU
Output
Output
Output
Output
Input
Function
Test Mode Initiate
This is the Test pin. Fix this pin to either Open or to the "H" level.
Bypass PLL for test
This input is used in the test mode. Fix this signal to the "H" level for the normal
operation.
Clock Generator Reset
This signal initializes the clock generator.
JTAG Reset Input
This signal is asynchronous reset input of the TAP Controller. This input has pull-down
device, however it is recommended to attach additional pull down resister to prevent
accidental assertion.
EJTAG Reset Input
This signal is asynchronous reset input of the Debugging Support Unit (DSU).
This input has pull-down device, however it is recommended to attach additional pull
down resister to prevent accidental assertion.
a measure such as connecting pull-up resistance to prevent this signal from low-level.
When this signal is deasserted, G-Bus time-out detection becomes invalid.
Note for tamper protection.
In production model, It is highly recommended to connect this terminal to low level right
under package without any routing on the motherboard.
JTAG or EJTAG Clock Input
During EJTRST is high level, this clock goes only to EJTAG TAP and EJTRST is low level,
it goes only JTAG TAP.
This is the JTAG clock input signal. JTDI or JTMS data is fetched at the rising edge of this
clock.
JTAG Command Input
This signal mainly controls the status shifts of the TAP Controller State Machine.
JTAG Data Input/Debugging Interrupt Input
When PC Trace mode is not selected, this signal is a JTAG Data input. This signal inputs
serial data to the JTAG Data/Instruction Registers.
When PC Trace mode is selected, this signal is an Interrupt input signal used to cancel PC
Trace mode for the debug unit.
JTAG Data Output/PC Trace Output
When PC Trace mode is not selected, this signal is a JTAG Data output. Data is output
by means of serial scan.
When PC Trace mode is selected, this signal outputs nonconsecutive program counter
values synchronous to DCLK.
This is the Interrupt input signal that is used for changing the Debugging Unit state from
the PC Trace mode to Off.
PC Trace Output
This signal outputs nonconsecutive program counter values synchronous to DCLK.
Debugging Clock Output
This signal is clock output for the real-time debugging system. When the PC Trace mode
is On, TPC[3:1] and the PCST signal are outputted synchronously. This clock is 1/3 the
frequency of the TX49/H4 Core operating clock (CPUCLK).
PC Trace Status Output
These signals output information such as the PC Trace Status.
TEST and EJTAG Debugging Interface
3-12
When connecting an EJTAG probe, take
Toshiba RISC Processor
TX4939
3
3