TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 293

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
14.3.3. External I/O DMA Transfer Mode
The External I/O DMA Transfer Mode performs DMA transfer with external I/O devices that are connected to the External
Bus Controller.
14.3.3.1. External Interface
External I/O devices signal DMA requests to the DMA Controller by asserting the DMA Transfer Request Signal
(DMAREQ[n]). On the other hand, the DMA Controller accesses external I/O devices by asserting the DMA Transfer
Acknowledge Signal (DMAACK[n]).
The DMA Transfer Request signal (DMAREQ[n]) can use the Request Polarity bit (REQPOL) of the DMA Channel Control
Register (DMCCRn) to select the signal polarity for each channel, and can use the Edge Request bit (EGREQ) to select
either edge detection or level detection for each channel. The DMA Transfer Acknowledge signal (DMAACK[n]) can also
use the Acknowledge Polarity bit (ACKPOL) to select the polarity.
Please assert/deassert the DMAREQ[n] signal as follows below.
When level detection is set (DMCCRn.EGREQ = 0)
Also, the DMAREQ[n] signal must be deasserted before the CE*/CS* signal is deasserted. If this signal is asserted too
soon, DMA transfer will not be performed. If this signal is asserted or deasserted too late, unexpected DMA transfer may
result.
currently asserting DMAACK[n], then deasserting DMAREQ[n].
When edge detection is set (DMCCRn.EGREQ = 1)
Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted after the DMAACK[n] signal
corresponding to a previously asserted DMAREQ[n] signal is deasserted. The DMAREQ[n] signal will not be detected even
if it is asserted before DMAACK[n] is deasserted.
*** is a timing diagram that shows the timing of external DMA access. In this timing diagram, both the DMAREQ[n] signal
and the DMAACK[n] signal are set to Low active (DMCCRn.REQPL = 0, DMCCRn.ACKPOL = 0).
The DMAACK[n] and DMADONE[n] signals, which are DMA control signals, are synchronized to SDCLK. When these
signals are used by an external I/O device that is synchronous to SYSCLK, it is necessary to take clock skew into account.
The DMAACK[n] signal is asserted either at the SYSCLK cycle, the same as with assertion of the CE*/CS* signal, or before
that. In addition, it is deasserted after the last ACK*/READY signal is deasserted.
When the DMADONE* signal (refer to 14.3.3.3) is used as an output signal, it is asserted for at least one SYSCLK cycle
while the DMAACK[n] signal is asserted either during the same SYSCLK cycle that the CE*/CS* signal is deasserted or
during a subsequent SYSCLK cycle. When the DMADONE* signal is used as an input signal, it must be asserted for one
SYSCLK cycle while the DMAACK[n] signal is being asserted.
14.3.3.2. Dual Address Transfer
If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices and to external memory is
each performed continuously. Each access is the same as normal access except when the DMAACK[n] signal is asserted.
Please refer to “14.3.8 Dual Address Transfer” for information regarding setting the register.
14.3.3.3. DMADONE* Signal
The DMADONE* signal operates as either the DMA stop request input signal or the DMA done signalling output signal, or
may operate as both of these signals depending on the setting of the DONE Control Field (DNCTRL) of the DMA Channel
Control Register (DMCCRn).
The DMADONE* signal is shared by four channels. The DMADONE* channel is valid for a channel when the DMAACK[n]
signal for that channel is asserted.
If the DMADONE* channel is set to be used as an output signal (DMCCRn.DNCTRL = 10/11), it will operate as follows
depending on the setting of the Chain End bit (CHDN) of the DMA Channel Control Register (DMCCRn).
Rev. 3.1 November 1, 2005
The DMAREQ[n] signal must be continuously asserted until one SYSCLK cycle after the DMAACK[n] signal is asserted.
During Dual Address transfer, we recommend detecting assertion of the CE* signal for the external I/O device that is
14-5
Toshiba RISC Processor
TX4939
14
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