TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 241

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.5.6. NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028
Rev. 3.1 November 1, 2005
Bits
31 : 8
7 : 4
3 : 0
7
Mnemonic
⎯
HOLD
SPW
Figure 10-14 NAND Flash Memory Strobe Pulse Width Register (NDFSPR)
6
Table 10-9 NAND Flash Memory Strobe Pulse Width Register (NDFSPR)
HOLD
1111
R/W
Field Name
Reserved
Hold Time
Strobe Pulse
Width
5
Description
⎯
Hold Time (Default: 1111)
This value defines the number of clock cycle from NDWE* or NDRE* de-assertion to
SADB [15:0] bus and SA [5:0] bus release. This means so called hold-time for
NAND write access with NDWE* signal.
Actual hold time will be given as follows:
Strobe Pulse Width (Default: 1111)
This value defines the number of clock cycle for NDWE* or NDRE* assertion pulse
width.
Actual pulse width will be given as follows:
4
Actual Hold Time = (HOLD + 1) x Period (GBUSCLK)
Pulse Width of NDWE* = (SPW) x Period (GBUSCLK)
Pulse Width of NDRE* = (SPW+1) x Period (GBUSCLK)
where the value SPW should not be zero (which is reserved), and
Period (GBUSCLK) = Period of GBUSCLK
where the value HOLD should not be zero (which is reserved), and
Period (GBUSCLK) = Period of GBUSCLK
HOLD=1 with 200MHz GBUSCLK (period=5ns) results 10ns Hold Time
Need to consider delay time of an external Latch Device to determine HOLD Time
SPW=6 at 200MHz GBUSCLK (period=5ns) results 35 ns pulse width for
NDRE* (read) and 30ns for NDWE* (write)
10-17
3
2
SPW
1111
R/W
Toshiba RISC Processor
1
0
TX4939
: Default
: Type
10
10