TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 25

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Table 12-6 Current Descriptor Pointer Register (CDESPtr) ................................................................................ 12-12
Table 12-7 Bus Error Address Register (BusErr) ................................................................................................. 12-13
Table 12-8 VPC Descriptor Table......................................................................................................................... 12-14
Table 12-9 Input Source Address Descriptor ....................................................................................................... 12-14
Table 12-10 Next Descriptor Pointer Descriptor................................................................................................... 12-14
Table 12-11 Control 1 Descriptor ......................................................................................................................... 12-14
Table 12-12 Control 2 Descriptor ......................................................................................................................... 12-15
Table 13-1 Divide Value and Count (IMBUSCLK = 100 MHz) .............................................................................. 13-4
Table 13-2 Timer Register List ............................................................................................................................. 13-10
Table 13-3 Timer Control Register ........................................................................................................................13-11
Table 13-4 Timer Interrupt Status Register .......................................................................................................... 13-12
Table 13-5 Compare Register A........................................................................................................................... 13-14
Table 13-6 Compare Register B .......................................................................................................................... 13-15
Table 13-7 Interval Timer Mode Register ............................................................................................................. 13-16
Table 13-8 Divide Register .................................................................................................................................. 13-17
Table 13-9 Pulse Generator Mode Register ........................................................................................................ 13-18
Table 13-10 Watchdog Timer Mode Register....................................................................................................... 13-19
Table 13-11 Timer Read Register n ..................................................................................................................... 13-20
Table 14-1 DMA Controller Transfer Modes........................................................................................................... 14-4
Table 14-2 Channel Register Setting Restrictions During Single Address Transfer ............................................... 14-8
Table 14-3 Channel Register Setting Restrictions During Dual Address Transfer............................................... 14-10
Table 14-4 DMA Command Descriptors ............................................................................................................. 14-15
Table 14-5 DMA Controller 0 Registers .............................................................................................................. 14-20
Table 14-6 DMA Controller 1 Registers ............................................................................................................... 14-21
Table 14-7 DMA Master Control Register ............................................................................................................ 14-22
Table 14-8 DMA Channel Control Register .......................................................................................................... 14-24
Table 14-9 DMA Channel Status Register ........................................................................................................... 14-28
Table 14-10 DMA Source Address Register ........................................................................................................ 14-30
Table 14-11 DMA Destination Address Register .................................................................................................. 14-31
Table 14-12 DMA Chain Address Register ......................................................................................................... 14-32
Table 14-13 DMA Source Address Increment Register........................................................................................ 14-33
Table 14-14 DMA Destination Address Increment Register ................................................................................. 14-34
Table 14-15 DMA Count Register ........................................................................................................................ 14-35
Table 14-16 DMA Memory Fill Data Register....................................................................................................... 14-36
Table 15-1 DDR Mapping Window Control .......................................................................................................... 15-13
Table 15-2 DDR Mapping Window Control .......................................................................................................... 15-14
Table 15-3 Supported DDR SDRAM Configration ............................................................................................... 15-16
Table 15-4 Interrupt Parameter Definition ............................................................................................................ 15-34
Table 16-1 Restrictions TX4939 in Satellite Mode ................................................................................................. 16-5
Table 16-2 PCI BOOT Related Register Assignment............................................................................................. 16-5
Table 16-3 Supported PCI Bus Commands .......................................................................................................... 16-8
Table 16-4 Initiator Access Space Address Mapping Register ............................................................................ 16-10
Table 16-5 Initiator Access Space Properties Register ........................................................................................16-11
Table 16-6 Corresponding of Memory Space Size and MSS[31:20] Value .......................................................... 16-12
Table 16-7 Target Access Space Address Mapping Register.............................................................................. 16-13
Table 16-8 Target Access Space Properties Register ......................................................................................... 16-13
Table 16-9 DMA Command Descriptors ............................................................................................................. 16-18
Table 16-10 PDMAC Interrupts............................................................................................................................ 16-20
Table 16-11 Power Management Interrupts ......................................................................................................... 16-20
Table 16-12 Error Detection Interrupts................................................................................................................. 16-20
Table 16-13 PCI Controller Control Register....................................................................................................... 16-25
Table 16-14 ID Registers .................................................................................................................................... 16-27
Table 16-15 PCI Status, Command Register ...................................................................................................... 16-28
Table 16-16 Class Code, Revision ID Register................................................................................................... 16-30
Table 16-17 PCI Configuration 1 Register .......................................................................................................... 16-31
Table 16-18 P2G Memory Space (m) PCI Lower Base Address Register (m=0,1,2) ........................................... 16-32
Table 16-19 P2G Memory Space (m) Configuration (m=0,1,2)............................................................................ 16-33
Table 16-20 Corresponding of Memory Space Size and MSS[31:20] Value ........................................................ 16-33
Table 16-21 P2G I/O Space PCI Base Address Register.................................................................................... 16-34
Table 16-22 Subsystem ID Register ................................................................................................................... 16-35
Table 16-23 Capabilities Pointer Register........................................................................................................... 16-35
Table 16-24 PCI Configuration 2 Register .......................................................................................................... 16-36
Table 16-25 G2P Timeout Count Register .......................................................................................................... 16-37
Table 16-26 G2P Status Register ....................................................................................................................... 16-37
Table 16-27 G2P Interrupt Mask Register........................................................................................................... 16-38
Table 16-28 Satellite Mode PCI Status Register .................................................................................................. 16-39
xxi
Toshiba RISC Processor
TX4939