TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 321

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
14.4.7. DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)
Offset Address:
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Name
Name
Name
Name
Type
Type
Type
Type
Bit
63:24
23:0
Mnemonic
SADINC
63
47
31
15
DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3)
DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3)
62
46
30
14
Field Name
Reserved
Source Address
Increment
61
45
29
13
Figure 14-15 DMA Source Address Increment Register
RESERVED
Table 14-13 DMA Source Address Increment Register
60
44
28
12
59
43
27
11
Description
Source Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Source Address
Register (DMSARn). This value is a 24-bit two’s complement and indicates a
byte count.
Refer to “14.3.7.1” and “14.3.8.1 Channel Register Settings During Dual
Address Transfer” for more information.
58
42
26
10
57
41
25
9
14-33
SADINC[15:0]
RESERVED
RESERVED
56
40
24
8
R/W
55
39
23
7
54
38
22
6
53
37
21
5
SADINC[23:16]
52
36
20
4
Toshiba RISC Processor
R/W
51
35
19
3
50
34
18
2
49
33
17
1
TX4939
R/W
R/W
48
32
16
0
14
14

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