TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 588

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
Rev. 3.1 November 1, 2005
Bit
31:13
12
11
10
9
8
7
6:5
4:1
0
Mnemonic
RCS
TES
RTSSC
RSDE
TSDE
RTSTL
TBRK
Field
Name
Reserved
RTS
Signal
Control
Select
CTS
Signal
Control
Select
Reserved
RTS
Software
Control
Serial Data
Reception
Disable
Serial Data
Transmit
Disable
Reserved
RTS Active
Trigger
Level
Break
Transmissi
on
Description
RTS Control Select (Default: 0)
This field sets the reception flow control using RTS output signals.
0: Disable flow control using RTS signals.
1: Enable flow control using RTS signals.
This field is supported by SIO0 only.
CTS Control Select (Default: 0)
This field sets the transmission flow control using CTS input signals.
0: Disable flow control using CTS signals.
1: Enable flow control using CTS signals.
This field is supported by SIO0 only.
RTS Software Control (Default: 0)
This register is used for software control of RTS output signals.
0: Set the RTS signal to Low (can receive data).
1: Sets the RTS signal to High (transmission pause request)
This field is supported by SIO0 only.
Receive Serial Data Disable (Default: 1)
This is the Serial Data Disable bit. When this bit is cleared, data reception starts
after the start bit is detected. The RTS signal will not become High even if this bit
is cleared. (This field is supported by SIO0 only)
0: Enable (can receive data)
1: Disable (halt reception)
Transmit Serial Data Disable (Default: 1)
This is the Serial Data Transmission Disable bit. When this bit is cleared, data
transmission starts. When set, transmission stops after completing transmission
of the current frame.
0: Enable (can transmit data)
1: Disable (halt transmission)
RTS Trigger Level (Default: 0001)
The RTS hardware control assert level is set by the reception data stage count of
the Receive FIFO.
0000: Disable setting
0001: 1
1111: 15
This field is supported by SIO0 only.
Break Transmit (Default: 0)
Transmits a break. The TXD signal is Low while TBRK is set to “1”.
0: Disable (clear break)
1: Enable (transmit break)
:
Table 19-17 Flow Control Register
19-22
Toshiba RISC Processor
R/W
⎯
R/W
R/W
⎯
R/W
R/W
R/W
⎯
R/W
R/W
TX4939
19
19