TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 426

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
Rev. 3.1 November 1, 2005
Bit
9
8
7
6
5
4
3
2
1:0
Mnemonic
IRBER
G2PM0EN
G2PM1EN
G2PM2EN
G2PIOEN
TCAR
ICAEN
LCFG
Field Name
Bus Error
Response Setting
During Initiator
Read
Initiator Memory
Space 0 Enable
Initiator Memory
Space 1 Enable
Initiator Memory
Space 2 Enable
Initiator I/O Space
Enable
Target
Configuration
Access Ready
Initiator
Configuration
Access Enable
Load
Configuration
Data Register
Rsvd
Table 16-54 PCI Controller Configuration Register
Description
Initiator Read Bus Error Response (Default: 0x1)
Bus error responses on the G-Bus are controlled when the following
phenomena indicated by the PCI Status, Command Register (PICSTATUS)
and the G2P Status Register (G2PSTATUS) occur during initiator Read
access.
Detected Parity Error (PCISTATUS.DPE)
Received Master Abort (PCISTATUS.RMA)
Received Target Abort (PCISTATUS.RTA)
Initiator Detected TRDY Time Out Error (G2PSTATUS.IDTTOE)
Initiator Detected Retry Time Out Error (G2PSTATUS.IDRTOE)
1: Responds with a Bus error on the G-Bus.
0:
(Normally terminates the Read transaction on the G-Bus. Read data is
invalid.)
Initiator Memory Space 0 Enable (Default: 0x0)
Controls PCI initiator access to Memory Space 0.
1: Memory Space 0 is valid.
0: Memory Space 0 is invalid.
Initiator Memory Space 1 Enable (Default: 0x0)
Controls PCI initiator access to Memory Space 1.
1: Memory Space 1 is valid.
0: Memory Space 1 is invalid.
Initiator Memory Space 2 Enable
Default: 0x0 (not PCI boot mode)
Default: 0x1 (PCI boot mode)
Controls PCI initiator access to Memory Space 2.
1: Memory Space 2 is valid.
0: Memory Space 2 is invalid.
Initiator I/O Space Enable (Default: 0x0)
Controls PCI initiator access to the I/O Space..
1: I/O Space is valid.
0: I/O Space is invalid.
Target Configuration Access Ready
Satellite mode:
Default:
PCI controller receives a target access, when this bit is 1 and
PCISTATUS.E2PDONE bit is 1. Configuration access from the PCI Bus can
be accepted during PCI Boot up after initialization from EEPROM or after
each initialization ends. Please use the software to set this bit after
initialization ends. Retry response to PCI configuration access is performed
until this bit is set.
1: Responds to PCI target access.
0: Performs a Retry response to PCI target access.
Host mode:
Default:0x0
The TX4939 will perform a Retry response when this bit is not set.
Initiator Configuration Access Enable (Default: 0x1)
Controls initiator PCI configuration access using the G2P Configuration
Address Register (G2PCFGADRS) and the G2P Configuration Data Register
(G2PCFGDATA). This is a diagnostic function.
1: Initiator configuration access is possible.
0: Initiator configuration access is not possible.
Load PCI Configuration Data Register (Default: 0x0)
When a software reset is performed on this bit using the Software Reset bit
(PCICFG.SRST) when this bit is already set, data is loaded to the
Configuration Space Register from the Configuration Data 0/1/2/3 Register.
1: Load from the Configuration Data 0/1/2/3 Register.
0: Load from EEPROM.
Does not respond with a Bus error on the G-Bus.
0x1 - when in PCI Boot mode
0x0 - when not in PCI Boot mode
16-62
Toshiba RISC Processor
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
TX4939
16
16