TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 584

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
Rev. 3.1 November 1, 2005
Bit
31:16
15
14
13
12
11
10
9
8
7
6
5
4:0
Mnemonic Field Name
UBRK
UVALID
UFER
UPER
UOER
ERI
TOUT
TDIS
RDIS
STIS
RFDN
Reserved
Receive
Break
Receive
FIFO
Available
Status
Frame Error
Parity Error
Overrun Error
Reception
Error
Interrupt
Reception
Time Out
Transmission
Data Empty
Reception
Data Full
Status
Change
Reserved
Reception
Data Stage
Status
Description
SIO Break (Default: 0)
This field indicates the break reception status of the next data in the
Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO)
updates the status.
0: No breaks
1: Detect breaks
SIO Available Data (Default: 1)
This field indicates whether or not data exists in the Receive FIFO
(SIRFIFO).
0: Data exists in the Receive FIFO.
1: No data exists in the Receive FIFO.
SIO Frame Error (Default: 0)
This field indicates the frame error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no frame errors.
1: There are frame errors.
SIO Parity Error (Default: 0)
This field indicates the parity error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO)
updates the status.
0: There are no parity errors.
1: There are parity errors.
SIO Overrun Error (Default: 0)
This register indicates the overrun status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no overrun errors.
1: There are overrun errors.
Receive Data Error Interrupt (Default: 0)
This bit is immediately set to “1” when a reception error (Frame Error,
Parity Error, or Overrun Error) is detected.
Time Out (Default: 0)
This bit is set to “1” when a reception time out occurs.
Transmit DMA/Interrupt Status (Default: 1)
This bit is set when available space of the amount set by the Transmit
FIFO Request Trigger Level (TDIL) of the FIFO Control Register (SIFCR)
exists in the Transmit FIFO.
Receive DMA/Interrupt Status (Default: 0)
This bit is set when valid data of the amount set by the Receive FIFO
Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is
stored in the Receive FIFO.
Status Change Interrupt Status (Default: 0)
This bit is set when at least one of the interrupt statuses selected by the
Status Change Interrupt Condition field (STIE) of the DMA/Interrupt
Control Register (SIDICR) becomes “1”.
Receive FIFO Data Number (Default: 00000)
This field indicates how many stages of reception data remain in the
Receive FIFO
(0 – 16 stages).
Table 19-11 DMA/Interrupt Status Register
19-18
Toshiba RISC Processor
Read/Write
⎯
R
R
R
R
R
R/W0C
R/W0C
R/W0C
R/W0C
R/W0C
⎯
R
TX4939
19
19