TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 320

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.6. DMA Chain Address Register (DM0CHARn, DM1CHARn)
Offset Address:
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Name
Name
Name
Name
Bit
63:36
35:3
2:0
Type
Type
Type
Type
Mnemonic
CHADDR
63
47
31
15
DMAC0 0xB000 (ch. 0) / 0xB040 (ch. 1) / 0xB080 (ch. 2) / 0xB0C0 (ch. 3)
DMAC1 0xB800 (ch. 0) / 0xB840 (ch. 1) / 0xB880 (ch. 2) / 0xB8C0 (ch. 3)
62
46
30
14
Field Name
Reserved
Chain Address
Reserved
61
45
29
13
60
44
28
12
Figure 14-14 DMA Chain Address Register
Table 14-12 DMA Chain Address Register
59
43
27
11
Description
Chain Address (Default: undefined)
When Chain DMA transfer is executed, this register sets the physical address
of the next DMA Command Descriptor to be read. If DMA transfer according
to the current Channel Register setting ends and the Chain Enable bit
(DMCCRn.CHNEN) is set, then the DMA Command Descriptor is loaded in
the Channel Register starting from the address indicated by this register.
When a value other than “0” is set in this register, the Chain Enable bit
(DMCCRn.CHNEN) and the Transfer Active bit (DMCCRn.XFACT) are set.
When “0” is set in this register, only the Chain Enable bit (DMCCRn.CHNEN)
is cleared.
When the Chain Address field value reads a DMA Command Descriptor of 0,
the value of this register is not updated and the value before that one
(address of the Data Command Descriptor when the value of the Chain
Address field being read was “0”) is held.
RESERVED
58
42
26
10
CHADDR[15:3]
57
41
25
9
14-32
R/W
⎯
CHADDR[31:16]
RESERVED
56
40
24
8
R/W
⎯
55
39
23
7
54
38
22
6
53
37
21
5
52
36
20
4
Toshiba RISC Processor
51
35
19
3
CHADDR[35:32]
50
34
18
2
RESERVED
R/W
⎯
49
33
17
1
R/W
⎯
R/W
R/W
TX4939
48
32
16
0
14
14