TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 268

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Video Port
12.3.8. Big Endian Support
VPC is designed to process data in 64-bit(double word) chunk in Little Endian format. Byte ordering within a double word in
Little Endian format is shown below:
For output mode, VPC will transmit byte data from byte 0 to byte 7 starting from address 0x00000000 then address
0x00000008.
Data output seen on VD[7:0] would be
a b c d e f g h I j k l m n o p q
For input mode, VPC will pack the byte data received from byte 0 to byte 7 to form a double word to write to system memory.
In Big Endian mode, VPC assumes byte ordering is reverse that of Little Endian format:
VPC has byte swapper logic to swap these byte data to Little Endian format before processing. There is one swapper for
output and one swapper for input. The input and output swappers are both off normally in Little Endian mode and is turned
on automatically when Big Endian mode is selected at the 4939 chip level. The CSR register has 2 bits, SWAPI and
SWAPO, to allow software to turn these 2 swappers on or off independently as shown in the tables below.
Rev. 3.1 November 1, 2005
SWAPI
Input Swapper
Byte #
Address 0x00000000 h g f e d c b a
Address 0x00000008 p o n m l k j i
Byte #
Address 0x00000000 a b c d e f g h
Address 0x00000008 I j k l m n o p
SWAPO
Output Swapper
12-16
Little Endian Big Endian
Little Endian Big Endian
off
off
0
0
7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7
on
on
1
1
on
on
0
0
off
off
1
1
Toshiba RISC Processor
TX4939
12
12

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