TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 315

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
DMA
Rev. 3.1 November 1, 2005
Bit
9
8
7:6
5
4:2
1
0
Mnemonic
CHNEN
XFACT
SMPCHN
XFSZ
MEMIO
SNGAD
Field Name
Chain Enable
Transfer Active
Reserved
Simple Chain
Transfer Set Size Transfer Set Size (Default: 000)
Memory to I/O
Single Address
Table 14-8 DMA Channel Control Register
Description
Chain Enable (Default: 0)
This bit indicates whether Chain operation is being performed. Read Only.
This bit is cleared when either the Master Enable bit (DMMCR.MSTEN) is
cleared or the Channel Reset bit (DMCCRn.CHRST) is set. This bit is set if a
value other than “0” is set when the CPU writes to the DMA Chain Address
Register (DMCHARn) or when a Chain transfer writes DMA Command
Descriptor. This bit is then cleared when “0” is set to the DMA Chain Address
Register (DMCHARn).
1: If transfer completes due to the current DMA Channel Register setting, a
DMA Command Descriptor is loaded in the DMA Channel Register from the
specified DMA Chain Address Register (DMCHARn) address, then DMA
transfer continues.
0: Further transfer does not start even if transfer completes due to the current
DMA Channel Register setting.
Transfer Active (Default: 0)
DMA transfer is performed according to the DMA Channel Register setting
when this bit is set. This bit is automatically set when a value other than “0” is
set in the DMA Chain Address Register (DMCHARn). DMA transfer is then
initiated. This bit is automatically cleared either when DMA transfer ends
normally it is stopped due to an error.
1: Perform DMA transfer.
0: Do not perform DMA transfer.
Simple Chain (Default: 0)
This bit selects the DMA Channel Register that loads data from DMA
Command Descriptors during Chain DMA transfer.
1: Data is only loaded to the four following DMA Channel Registers: the Chain
Address Register (DMCHARn), the Source Address Register (DMSARn), the
Destination Address Register (DMDARn), and the Count Register
(DMCNTRn).
0: Data is loaded to all eight DMA Channel Registers.
These bits set the transfer data size of each bus operation in the internal bus.
When the transfer set size is set to four double words or greater, the data size
actually transferred during a single bus operation does not always match the
transfer set size. Refer to “14.3.7.2” and “14.3.8.2 Burst Transfer During Dual
Address Transfer” for more information.
000: 1 byte
001: 2 byte
010: 4 byte
011: 8 bytes (1double word)
100: 4 double words
101: 8 double words
110: 16 double words (Single Address transfer only)
111: 32 double words (Single Address transfer only)
Memory to I/O (Default: 0)
This bit specifies the transfer direction during Single Address transfer
(DMCCRn.SNGAD = 1). Clear this bit when in the Memory Fill Transfer
mode.
The setting of this bit is ignored when Dual Address transfer is set
(DMCCRn.SNGAD = 0).
1: From memory to I/O
0: From I/O to memory
Single Address (Default: 0)
This bit specifies whether the transfer method is Single Address transfer or
Dual Address transfer.
1: Single Address transfer
0: Dual Address transfer
14-27
Toshiba RISC Processor
R/W
R
R/W
R/W
R/W
R/W
R/W
TX4939
14
14

Related parts for TX4939XBG-400