TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 695
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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CRYPT
Rev. 3.1 November 1, 2005
Bit(s)
18
17
16
15:13
12:11
10
9
8
7:6
5
4
3
2
1
0
Field
DCINT
-
GBINT
INDXAST
CSWAP
--
CDIV
--
PDINT
--
--
GINTE
RSTD
RSTC
ENCR
R/W
RO
-
RO
RO
R/W
--
R/W
--
R/W
--
--
R/W
R/W
R/W
R/W
Default
0
-
0
0
00
0
0
0
01
0
0
0
0
0
0
Table 26-2 Control and Status Register (CSR)
Description
DMA Completion Interrupt
0: No interrupt
1: Transfer complete
This bit will be clear after read.
Reserved
G-Bus Error Interrupt
0: No interrupt
1: G-Bus error
This bit will be clear after read.
Operate Index A Indicator
This field indicates the current operate index A register set
Cipher Swap option
00: Normal
01: Swap Input data (for testing only)
10: Swap Output data (for testing only)
11: Swap both Input and Output data (for testing only)
When = 2’b00, sysBigEndian control the swap logic.
two bits control the swap logic.
Reserved.
modular exponentiation operation coprocessor engine clock select
0: Div 2 (GBUSCLK DIV2)
1: Div 1 (same as GBUSCLK)
Reserved.
Programmable DMA Completion Interrupt
00: Interrupt for every descriptor at completion of transfer.
01: Interrupt only when Next Descriptor pointer = Null or when “End_packet” bit
set at completion of transfer.
10: Interrupt only when Next Descriptor pointer = Null at completion of transfer.
11: Disable DMA Completion Interrupt
Reserved.
Reserved.
Interrupt Enable
0: Disable All Interrupts.
1: Enable All Interrupts.
This bit has to be program before start Cipher engine
Reset DMA Controller
0: Normal
1: Reset
After set this bit, need to reset it back to “0” for normal operation.
Reset Cipher engine
0: Normal
1: Reset
After set this bit, need to reset it back to “0” for normal operation.
Start Cipher Engine
0: Idle
1: Start
When write “1” to this bit, Cipher engine will begin to operate.
26-5
000
001
010
……..
110
111
Operating with Context register set #6
Engine idle
Operating with Context register set #1
Operating with Context register set #2
Reserved
……………………..
Toshiba RISC Processor
Other selection,
TX4939
these
26
26
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