TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 197
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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EBC
9.2.7.3.
When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by Ready input from an external
device. Ready input is internally synchronized. Refer to Section “9.2.8.5 Ready Input Timing” for more information
regarding timing.
When the Wait cycle count specified by EBCCRn.PWT:WT elapses, a check is performed to see whether the Ready signal
was asserted. Since EBCCRn.WT[0] is used to indicate the ACK*/ Ready Static/Dynamic mode, it is not used for setting the
Wait cycle count. Therefore, the Wait cycle count that can be set by the Ready mode is 0, 2, 4, 6 … 62. The Ready mode
does not support Burst access by the internal bus.
9.2.7.4.
When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic mode. When it is in the
ACK*/Ready Static mode, the ACK*/Ready signal becomes HiZ. Wait cycles are inserted into the access cycle according
to the values of EBCCRn.PWT and EBCCRn.WT. The Wait cycle count in the first access cycle of Single access or Burst
access is determined by the EBCCRn.WT value. The Wait cycle count can be set from 0 to 15. The Wait cycle count of
subsequent Burst cycles is determined by the EBCCRn.PWT value. The Wait cycle count can be set from 0 to 3.
Rev. 3.1 November 1, 2005
ACK*/READY
ACK*/READY
SWE*/BWE*
SWE*/BWE*
SADB [15:0]
SADB [15:0]
AD [28:6]
AD [21:6]
SYSCLK
SYSCLK
SA [5:0]
SA [5:0]
output
ACE*
input
ACE*
Ready Mode
Page Mode
OE*
OE*
CE*
CE*
0
0
1
1
EBCCRn.PWT:WT=2
0
0
EBCCRn.WT=2
2
2
1
3
1
3
4
2
4
2
Figure 9-4 Ready Mode (ACEHOLD=0)
Figure 9-5 Page Mode (ACEHOLD=0)
5
5
Ready Mode (ACEHOLD=0)
Page Mode (ACEHOLD=0)
EBCCRn. PWT=1
6
6
0
7
7
1
9-7
8
8
EBCCRn. PWT=1
9
9
0
10
10
1
EBCCRn.PWT:WT=2
11
11
0
EBCCRn. PWT=1
12
12
1
0
13
13
2
1
14
14
Toshiba RISC Processor
15
15
16
16
17
17
18
18
19
19
TX4939
Rev 2.13
Rev 2.13
9
9
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