TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 513

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.3.8.1.1. Format of Recipient Addresses
Bit 0 of a recipient address specifies the address type. This bit indicates whether the address is an individual address or
a group address. Group addresses are also referred to as multicast addresses. Individual addresses are also referred to
as unicast addresses. Broadcast addresses are special group addresses that are FF-FF-FF-FF-FF-FF hexadecimal
addresses.
Bit 1 distinguishes locally managed addresses from globally managed addresses. If an address is managed globally
(universal), bit 1 is set to "0". If an address is allocated locally, bit 1 is set to "1". Bit 1 is set to "1" for broadcast addresses.
Recipient address (first Byte)
Rev. 3.1 November 1, 2005
Bit(s)
7 : 2
1
0
Cyclic redundancy check (CRC)— 4 Bytes
Also referred to as the frame check sequence (FCS), this value is calculated from all other fields except the
preamble, SFD, and CRC itself.
The preamble, SFD, pad data, and CRC are added on by the transmission side. You can also pad data using
the software. CRC can use the Transmission Control Register to suppress padding. You can use the Reception
Control Register to control deletion of CRC. You can delete pad data using either the DMA engine or the
software driver.
Except for CRC, the MAC transmits each byte starting from the least significant byte. In this document, all bytes
transmitted or received are collectively referred to as “packets”. The term “frame” refers to a part that you
provide during transmission or a part that is provided to you during reception.
Standard IEEE802.3 frames are transformed by various factors and options.
Depending on the PHY, there are cases where the preamble length is not 7 Bytes. Sometimes a repeater
shortens the preamble. The transmission part sends the preamble in a standard format, but the reception part
does not care even if there is no preamble or the preamble is more than 7 Bytes long. SFD follows the preamble.
When in the Short Packet mode, LLC data less than 46 Bytes long is allowed. In this case, there are options for
suppressing padding when transmitting data or for allowing the reception of short packets.
When in the Long Packet mode, LLC data larger than 1500 Bytes is allowed. There is an option for allowing the
reception of long packets.
There is an option for suppressing the addition of CRC fields.
There is also an option for allowing the reception of packets that do not have a valid CRC field.
Mnemonic
Rest
U/L
I/G
Field Name
Remaining Bit
Universal/Local
Individual/Group
Figure 18-11 Format of Recipient Addresses
Description
Rest
Remaining bits of the first Byte are the recipient bits.
U/L
0: Universal address
1: Local address
I/G
0: Individual address
1: Group address
18-21
7
Rest
Toshiba RISC Processor
2
U/L
1
I/G
TX4939
0
18
18

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