TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 718

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Electrical
28.3. DC Characteristics
28.3.1. DC Characteristics of Pins (Except PCI I/F)
Rev. 3.1 November 1, 2005
Low-level Input Voltage
High-level Input Voltage
Low-level Output Current
High-level Output Current
Reference Voltage
Low-level Input Voltage
High-level Input Voltage
Low-level Output Current
High-level Output Current
Low-level Input Leak Current
Low-level Input Leak Current
High-level Input Leak Current
High-level Input Leak Current
Hi-z Output Leak Current
Operating Power Supply
Current (Internal Power)
Operating Power Supply
Current (VDD33)
Operating Power Supply
Current (VDD25)
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V or VDD25 = 2.6 V ± 0.1 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Those values are programmable.
Item
All input pins, all bi-directional pins (during input) except for PCI/DDR Interface signals.
TIMER[1:0], TXD, SADB[15:0], DCLK, PCST[8:0], TDO, TPC[3:1]
DDR input and bi-directional signals. DRDQ[31:0], DRDQS[3:0], DRCKREF
DDR output and bi-directional signals. DRA[13:0], DRDQ[31:0], DRDQS[3:0], DRDM[3:0],
DRCS[1:0]*, DRCKP, DRCKM, DRCKOUT, DRBA[1:0], DRWE*, DRCAS*, DRRAS*, DRCKE
All input without Pull-Up device include bi-directional during input, such as MSTCLK, MSTCLK2,
RESET*, DRDQ[31:0], DRDQS[3:0], DRCKREF, All ATA100 signals, NDRB*, WAIT, GPIO[3:0],
All PCI Signals, BITCLK, All ACLINK or I2S signals, I2C_D0, TRST*, EJRST*, DINT*
All input with Pull-Up device include bi-directional during input, such as All Video Port Signals,
SADB[15:0], SA[5:0], ACK*, DMAREQ[2:0], DMAACK[2:0], DMADONE*, NDLA, All SPI signal,
RXD[3:0], NMI*, INT[2:0]*, INT[D:A]*, TEST[0]*, BYPASSPLL, div_RST*, TCK, TMS, TDI, DINT*
All input without Pull-Down device include bi-directional during input, such as, MSTCLK, MSTCLK2,
HALTDOZE, DRDQ[31:0], DRDQS[3:0], DRCKREF, All Video Port signals, All ATA100 signals, All
input of EBC signals, NDRB*, WAIT, GPIO[3:0], All PCI signals, BITCLK, I2S_WS0, I2S_SCK0,
I2S_WS1, I2S_SCK1, I2S_WS, I2S_SCK, I2S_SD1, I2C_DO, All SPI signals, RXD[3:0], NMI*,
INT[2:0]*, INT[D:A]*, TEST[0]*, BYPASSPLL*, div_RST*, TCK, TMS, TDI, DINT*,
All input with Pull-Down device include bi-directional during input, SDIN[1:0], I2S_SD0(I2S 2ch),
I2S_SD1(I2S 2ch), I2S_SD0(I2S 5.1ch), I2S_SD2(I2S 5.1ch), TRST*, EJRST*
TXD[3:0], All ATA100 signals, ALARM*
ACE*, SA[5:0], BE[1:0]*, CE[7:0]*, DMAACK[2:0], DMADONE*, HALTDOZE, SWE*, SYSCLK,
Symbol
I
I
Vref
I
V
V
CCIO1
CCIO2
V
I
I
V
I
I
CCInt
I
I
I
I
I
OH1
OH2
OL1
OL2
IH1
IH2
IL1
IL2
OZ
IH1
IH2
IL1
IL2
(Note 1)
(Note 1)
(Note 2) V
(Note 2) V
DRVref1, VDD25 = 2.5V or 2.6V
(Note 3) VDD25 = 2.5V or 2.6V
(Note 3) VDD25 = 2.5V or 2.6V
(Note 4) V
(Note 4) V
(Note 5) V
(Note 6) V
(Note 7) V
(Note 8) V
(Note 9)
VDD33 = 3.3 V,
VDD25 = 2.6 V
VDDC = 1.3 V,
CPU Clock = 400 MHz
DDR Clock = 200 MHz
Pin Load Capacitance = 25 pF
OL
OH
OL
OH
IN
IN
IN
IN
Condition
=VSS
=VSS
=VDD33
=VDD33
=0.4V
=0.4V
=2.4V
=1.8V
28-2
0.49*VDD25
Vref+0.15
Note 10
T.B.D.
T.B.D.
T.B.D.
Min.
-200
-0.3
-0.3
2.0
-10
-10
-10
10
4
-
-
Toshiba RISC Processor
T.B.D.
T.B.D.
T.B.D.
Typ.
0.51*VDD25
VDD33+0.3
VDD25+0.3
Vref-0.15
Note 10
T.B.D.
T.B.D.
T.B.D.
Max.
200
-10
0.8
10
10
10
-4
TX4939
Unit
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
V
28
28