TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 395

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.4. PCI Configuration 1 Register (PCICFG1)
The following fields correspond to the following registers.
Rev. 3.1 November 1, 2005
Bit
31
30:24
23
22:16
15:8
7:0
Default
Default
NAME
NAME
TYPE
TYPE
Mnemonic
BISTC
MFUNS
HT
LT
CLS
□ BIST field
□ Header Type field
□ Latency Timer field
□ Cache Line Size field
BISTC
31
15
R
0
30
14
→
Field Name
BIST Capable
Reserved
Multi-Function
Header Type
Latency Timer
Cache Line Size
BIST Register of the PCI Configuration Space
29
13
→
→
Header Type Register in the PCI Configuration Space
28
12
→
Latency Timer Register of the PCI Configuration Space
0x00
R/W
LT
Cache Line Size Register of the PCI Configuration Space.
Reserved
Figure 16-17 PCI Configuration 1 Register
Table 16-17 PCI Configuration 1 Register
27
11
Description
BIST Capable (Fixed Value: 0)
Indicates that the BIST function is not being supported.
Multi-Function (Fixed Value: 0)
0: Indicates that the device is a single-function device.
Header Type (Default: 0x00)
Indicates the Header type.
0000000: Header Type 0
Latency Timer (Default: 0x00)
Sets the latency timer value. Specifies the PCI Bus clock count during which
to abort access when the GNT* signal is deasserted during PCI access.
Since the lower two bits are fixed to “0”, cycle counts can only be specified in
multiples of 4.
Cache Line Size (Default: 0x00)
Is used to select the PCI Bus command during a Burst Read transaction. See
“16.3.6 Supported PCI Bus Commands” for more information.
26
10
25
9
16-31
24
8
MFUNS
23
R
0
7
22
6
21
5
20
Toshiba RISC Processor
4
0x00
CLS
R/W
0x00
R/L
HT
19
3
0xD00C
18
2
17
1
R/W
R
⎯
R
R/L
R/W
R/W
TX4939
16
0
16
16