TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 377

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word Swap (see16.3.10). Table
16-8 shows the settings registers for these properties.
When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size set by the Target
Pre-fetch Read Burst Length Field (P2GCFG.TPRBL) of the P2G Configuration Register during a PCI target Read
transaction. This is performed using accesses to resources that will not be affected even if a pre-read such as memory is
performed. Also, PCI Burst Reads to memory spaces that were set to I/O space and pre-fetch disable are not supported.
Note:
Rev. 3.1 November 1, 2005
Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
PCIAddr
PBASE
Always use PCI single reads. Don’t use burst reads.
Figure 16-9 Address Conversion for Target (PCI Bus (PCI Bus
n = 20 - 29 Memory Space 0, 1, 2
n = 8
GBusAddr
MemEnable: PCI State Command Register Memory Space bit (PCISTATUS.MEMSP)
GBASE
39/32
39/32
Space
Size
1 – 512MB 40-bit
1 – 512MB 40-bit
1 – 512MB 32-bit
256 B
I/O Space
PCICCFG.TCAR & MemEnable &
P2GM0GBASE.P2GM0EN
PCICCFG.TCAR & MemEnable &
P2GM1GBASE.P2GM1EN
PCICCFG.TCAR & MemEnable &
P2GM2GBASE.P2GM2EN
PCICCFG.TCAR & IOEnable &
P2GIOGBASE.P2GIOEN
IOEnable: PCI State Command Register I/O Space bit (PCISTATUS.IOSP)
Table 16-7 Target Access Space Address Mapping Register
35
PCI
Address
32-bit
35
Compare
Table 16-8 Target Access Space Properties Register
Enable
PCI Bus Base Address PBASE
P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:n]
P2GM1PUBASE.BA[39:32] | P2GM1PLBASE.BA[31:n]
P2GM2PUBASE.BA[39:32] | P2GM2PLBASE.BA[31:n]
P2GIOPBASE.BA[31:8]
n
n
n
n
P2GCFG.MEM0PD (valid)
P2GCFG.MEM1PD (valid)
P2GCFG.MEM2PD (invalid)
Always invalid
16-13
n-1
n-1
n-1
n-1
Pre-fetch (Initial State)
→
G-Bus Address Conversion)
P2GM0GBASE.BSWAP,
P2GM0GBASE.EXFER
P2GM1GBASE.BSWAP,
P2GM1GBASE.EXFER
P2GM2GBASE.BSWAP,
P2GM2GBASE.EXFER
P2GIOGBASE.BSWAP,
P2GIOGBASE.EXFER
Toshiba RISC Processor
G-Bus Base Address
GBASE
P2GM0GBASE.BA[35:n]
P2GM1GBASE.BA[35:n]
P2GM2GBASE.BA[35:n]
P2GIOGBASE.BA[35:8]
Endian Swap
0
0
0
0
TX4939
Rev 1.00
16
16