TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 299
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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DMA
14.3.8.2. Burst Transfer During Dual Address Transfer
The DMA Controller has a 64-bit 8-stage FIFO on-chip that is connected to the internal bus (G-Bus) for Burst transfer
during Dual Address transfer. Since this FIFO employs a shifter, it is possible to perform transfer of any address or data
size. Burst transfer is only performed when 4 Double Words or 8 Double Words is set by the Transfer Setting Size field
(DMCCRn.XFSZ) and the FIFO Use Enable bit (DMMCRn.FIFUM[n]) of the DMA Master Control Register is set.
According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst
transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not a
multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer
sizes that were specified by a Burst transfer. Therefore, it is necessary to divide the transfer into multiple Burst
transactions of a transfer size smaller than the specified transfer size. This division method changes according to the
seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control Register and whether or not the
address offset relative to the Transfer Setting size (DMCCRn.XFSZ) is equivalent to the source address and destination
address combined.
Figure 14-4 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “1”, the
lower 8 bits of the Transfer Start address for the transfer source are set to 0xA8, the lower 8 bits of the Transfer Start
address for the transfer destination are set to 0x38, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 Double
Words.
Transfer repeats according to the transfer setting size, regardless of the different address offsets. However, transfers that
span across 32-double word boundaries are divided. Since data remains in the on-chip FIFO when in this mode, it
becomes possible to share the on-chip FIFO among multiple DMA channels.
Figure 14-5 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “0”, the
lower 8 bits of the Transfer Start address for the transfer source are set to 0xA8, the lower 8 bits of the Transfer Start
address for the transfer destination are set to (a) 0x28/(b) 0x30, and the Transfer Setting Size (DMCCRn.XFSZ) is set to
8 double words.
Panel (a) of this figure shows when the address offset is equivalent. In this case, first transfer of three double words is
performed up to the address that is aligned with the transfer setting size. Then, transfer of eight double words that is
specified by the transfer setting size is repeated.
Rev. 3.1 November 1, 2005
a0
a8
b0
b8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
c0
c8
f0
f8
63
Source Address
Figure 14-4 Dual Address Burst Transfer (DMCCRn.USEXFSZ
0
FIFO (8 Double Words)
14-11
20
28
30
38
40
48
50
58
60
68
70
78
80
88
a0
a8
b0
b8
c0
c8
Toshiba RISC Processor
Destination Address
63
=
1)
0
TX4939
14
14
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