TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 582

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
Rev. 3.1 November 1, 2005
Bit
31:16
15
14
13
12
11
10:9
8:6
5:0
Mnemonic
TDE
RDE
TIE
RIE
SPIE
CTSAC
STIE
Field Name
Reserved
Transmit DMA
Transfer
Enable
Receive DMA
Transfer
Enable
Transmit Data
Empty
Interrupt
Enable
Reception
Data Full
Interrupt
Enable
Reception
Error Interrupt
Enable
CTSS Active
Condition
Reserved
Status
Change
Interrupt
Enable
Description
Transmit DMA Enable (Default: 0)
This field sets whether to use DMA in the method for writing transmission data to
the Transmit FIFO.
0: Do not use DMA.
1: Use DMA.
Receive DMA Enable (Default: 0)
This field sets whether to use DMA in the method for reading reception data from
the Receive FIFO.
0: Do not use DMA.
1: Use DMA.
Transmit Data Empty Interrupt Enable (Default: 0)
When there is open space in the Transmit FIFO, this field sets whether to signal
an interrupt. Set “0” when in the DMA Transmit mode (TDE = 1).
0:
FIFO.
1:
Receive Data Full Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when reception data is full
(SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs. Set to
“0” when in the DMA Receive mode (RDE = 1).
0:
occurred.
1:
occurred.
Receive Data Error Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when a reception error (Frame Error,
Parity Error, Overrun Error) occurs (SIDISR.ERI = 1).
0: Do not signal reception error interrupts.
1: Signal reception error interrupts.
CTSS Active Condition (Default: 00)
This field specifies status change interrupt request conditions using the CTS
Status (CTSS) of the Status Change Interrupt Status Register.
00: Do not detect CTS signal changes.
01: Rising edge of the CTS pin
10: Falling edge of the CTS pin
11: Both edges of the CTS pin
CTS pin is supported only for SIO0.
Status Change Interrupt Enable (Default: 0x00)
This field sets the set conditions of the Status Change bit (STIS) of the
DMA/Interrupt Status Register (SIDISR). The condition is selected depending on
which bit of the Status Change Interrupt Status Register (SISCISR) is set.
(Multiple selections are possible.)
An SIO interrupt is asserted when STIC is “1”.
000000: Do not detect status changes.
1*****:
*1****:
Active Condition field (CTSAC) in the CTS Status bit (CTSS).
**1***:
***1**:
****1*:
“1”.
*****1:
Table 19-9 DMA/Interrupt Control Register
Do not signal an interrupt when there is open space in the Transmit
Signal an interrupt when there is open space in the Transmit FIFO.
Do not signal interrupts when reception data is full/reception time out
Signal interrupts when reception data is full/reception time out
Set “1” to STIS when the Overrun bit (OERS) is “1”.
Set “1” to STIS when a change occurs in a condition set by the CTSS
Set “1” to STIS when the Break bit (RBRKD) becomes “1”.
Set “1” to STIS when the Transmit Data Empty bit (TRDY) becomes “1”.
Set “1” to STIS when the Transmission Complete bit (TXALS) becomes
Set “1” to STIS when the Break Detection bit (UBRKD) becomes “1”.
19-16
Toshiba RISC Processor
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
TX4939
19
19