TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 405

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.18. P2G Configuration Register (P2GCFG)
Rev. 3.1 November 1, 2005
Bit
31:23
22
21:20
19:16
15
14
13
12
11
10
9
8
7:0
Default
Default
NAME
NAME
TYPE
TYPE
Mnemonic
PME
TPRBL
FTRD
FTA
MEM0PD
MEM1PD
MEM2PD
TOBFR
TIBFR
FTRD
R/W
0x0
31
15
FTA
R/W
0x0
30
14
Field Name
Reserved
PME
Target Prefetch
Read Burst
Length
Reserved
Force Target
Retry/Disconnect
Force Target Abort Force Target Abort (Default: 0x0)
Reserved
Memory 0 Window
Prefetch Disable
Memory 1 Window
Prefetch Disable
Memory 2 Window
Space Prefetch
Disable
Target Out-Bound
FIFO Reset
Target In-Bound
FIFO Reset
Reserved
Rsvd MEM0PD MEM1PD MEM2PD TOBFR TIBFR
29
13
R/W
0x0
28
12
RESERVED
Figure 16-29 P2G Configuration Register
Table 16-30 P2G Configuration Register
R/W
0x0
27
11
Description
PME (Default: 0x0)
This bit is invalid since the PME* signal is an input signal.
Target Prefetch Read Burst Length (Default: 0x3)
These bits set the number of DWORDS (32-bit words) to be read into the data
FIFO when prefetching is valid during a target memory Read operation.
Extra data transferred to the data FIFO is deleted when performing a memory
Read operation of a PCI Bus transfer that is smaller than the set size.
This setting is invalid when prefetching is disabled.
0x00: Access and transfer each 2 DWORDs of data to the target read FIFO.
0x01: Access and transfer each 4 DWORDs of data to the target read FIFO.
0x10: Access and transfer each 6 DWORDs of data to the target read FIFO.
0x11: Access and transfer each 8 DWORDs of data to the target read FIFO.
Force Target Retry/Disconnect (Default: 0x0)
The PCI Controller executes Retry Termination on a PCI Read access
transaction if this bit is set to “1”. This is a diagnostic function.
The PCI Controller executes a Target Abort on a PCI Read access
transaction if this bit is set to “1”. This is a diagnostic function.
Memory 0 Window Prefetch Disable (Default: 0x0)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 0 Space
is disabled when this bit is set to “1”. PCI Burst Read transactions are not
supported when prefetching is disabled.
Memory 1 Window Prefetch Disable (Default: 0x0)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 1 Space
is disabled when this bit is set to “1”. PCI Burst Read transactions are not
supported when prefetching is disabled.
Even if the setting of this bit is changed, prefetchable bits in the Base Address
Register of the PCI Configuration Space will not reflect this change.
Memory 2 Window Prefetch Disable (Default: 0x1)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 2 Space
is disabled when this bit is set to “1”. PCI Burst Read transactions are not
supported when prefetching is disabled.
Even if the setting of this bit is changed, prefetchable bits in the Base Address
Register of the PCI Configuration Space will not reflect this change.
Target Out-Bound FIFO Reset (Default: 0x0)
The PCI Controller flushes the CORE internal Target Out-Bound FIFO when
“1” is written to this bit. This bit always reads out “0” when it is read. This is a
diagnostic function.
Target In-Bound FIFO Reset (Default: 0x0)
The PCI Controller flushes the CORE internal Target In-Bound FIFO when “1”
is written to this bit. This bit always read out “0” when it is read. This is a
diagnostic function.
R/W
0x1
26
10
R/W
0x0
25
9
16-41
R/W
0x0
24
8
23
7
R/W1S
PME
0x0
22
6
21
5
TPRBL
R/W
0x3
RESERVED
20
Toshiba RISC Processor
4
19
3
18
Reserved
2
17
1
R/W
⎯
R/W1S
R/W
⎯
R/W
R/W
⎯
R/W
R/W
R/W
R/W
R/W
⎯
TX4939
16
0
16
16