TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 443

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.61. PDMAC Control Register (PDMCFG)
Rev. 3.1 November 1, 2005
Bit
63:22
21
20
19:14
13:11
10
9
8
Default
Default
Default
Default
NAME
NAME
NAME
NAME
TYPE
TYPE
TYPE
TYPE
Mnemonic
RSTFIFO
EXFER
REQDLY
ERRIE
NCCMPIE
NTCMPIE
RESERVED
63
47
31
15
62
46
30
14
Field Name
Rsvd
Reset FIFO
Endian Transfer
Rsvd
Request Delay
Time
Error Detect
Interrupt Enable
Normal Chain
Complete
Interrupt Enable
Normal Data
Transfer
Complete
Interrupt Enable
61
45
29
13
REQDLY
R/W
0x0
60
44
28
12
Table 16-74 PDMAC Control Register
RESERVED
Figure 16-72 PDMAC Control Register
59
43
27
11
Description
Reset FIFO (Default: 0x0)
Initializes the Read pointer and Write pointer to the FIFO in the PDMAC, and
sets the FIFO hold count to “0”. Please use the software to clear this bit when
it is set.
This is a function for a diagnosis. Usually, it is not used.
1: Performs FIFO reset.
0: Does not perform FIFO reset.
Endian Transfer (Default: 0x0)
Specifies whether to perform Endian transfer. Please use the default as is.
Set up EXFER as follows according to a Endian setup of G-Bus.
1: G-Bus in Little Endian
0: G-Bus in Big Endian
Request Delay (Default: 0x0)
G-Bus transactions for DMA transfer must be performed separated at least by
the interval this field specifies.
000: Continuously try to perform G-Bus transfer.
001: 16 G-Bus clocks
010: 32 G-Bus clocks
011: 64 G-Bus clocks
100: 128 G-Bus clocks
101: 256 G-Bus clocks
110: 512 G-Bus clocks
111: 1024 G-Bus clocks
Interrupt Enable on Error (Default: 0x0)
1: PDMAC generates an error during error detection.
0: PDMAC does not generate an error during error detection.
Interrupt Enable on Chain Done (Default: 0x0)
1:
0:
complete.
Interrupt Enable on Transfer Done (Default: 0x0)
1:
complete.
0:
transfer is complete.
ERRIE NCCMPIE NTCMPIE CHNEN XFRACT Rsvd
R/W
0x0
58
42
26
10
PDMAC generates an interrupt when the current chain is complete.
PDMAC does not generate an interrupt when the current chain is
PDMAC generates an interrupt when the current data transfer is
PDMAC does not generate an interrupt when the current data
R/W
0x0
57
41
25
9
16-79
RESERVED
RESERVED
R/W
0x0
56
40
24
8
0x0
55
39
23
R
7
R/W
0x0
54
38
22
6
RSTFIFO EXFER
R/W
0x0
53
37
21
5
BSWAP
R/W
R/W
0x0
0x0
52
36
20
Toshiba RISC Processor
4
51
35
19
XFRSIZE
3
R/W
0x0
RESERVED
50
34
18
2
R/W
0x0
49
33
17
1
R/W
⎯
R/W
R/W
⎯
R/W
R/W
R/W
R/W
TX4939
R/W
0x1
48
32
16
0
16
16