TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 376

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.8. Target Access (PCI Bus → G-Bus Address Conversion)
During PCI target access, the PCI Bus address of the Bus transaction issued by the PCI Bus is converted into a G-Bus
address and is used to issue a Bus transaction on the G-Bus. 40-bit PCI Bus addresses are used on the PCI Bus. Also,
36-bit physical addresses are used on the G-Bus.
Three memory access windows and one I/O access window can be set in the PCI bus space (Figure 16-8).
When the Bus transactions to these access windows are issued on the PCI Bus, these Bus transactions are accepted as
PCI target devices. The PCI Bus Address is converted into G-Bus addresses, and then corresponding Bus transactions are
issued to the G-Bus.
The memory space window responds to the PCI memory space access command. The I/O space window responds to the
PCI I/O space access command.
Note:
mode, the order of bits in a 32-bit word does not change during a PCI transfer. (The byte ordering changes.)
When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[39:0]) into a G-Bus address (GBusAddr[35:0]) is
as follows below. GBASE[35:8], and PBASE[39:8] each represent the setting register of the corresponding access window
indicated below in Table 16-7. The “&” symbol indicates a logical AND for each bit, and “|” indicates bit linking.
Rev. 3.1 November 1, 2005
Note: MSS[31:20] Field locates inside the register of P2GM(m)CFG. See detail in 16.4.6
Memory space 0, 1, and 2
Note: Memory space 0,1 and 2 in the TX4939 has fixed bit linking as given below
I/O space
MSS[31:20]
0xFFC
0xFC0
0xFE0
0xFFE
0xFFF
Byte swapping is always disabled when prefetch mode is disabled. When the G-Bus is configured for big-endian
0xE00
0xF00
0xF80
0xFF0
0xFF8
0xFF_FFFF_FFFF
0x00_FFFF_FFFF
0x00_0000_0000
PCI IO Space
IO Access Window
Table 16-6 Corresponding of Memory Space Size and MSS[31:20] Value
31
1
1
1
1
1
1
1
1
1
1
30
1
1
1
1
1
1
1
1
1
1
If (PCIAddr[39:n] == P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:n] then
GbusAddr[35:0] = P2GM{X}GBASE[35:29]|PCIAddr[28:0], where X = 0,1,2
If (PCIAddr[31:8] == P2GIOPBASE.BA[31:8]) then
GBusAddr[35:0] = P2GM0GBASE[35:n] | PCIAddr[(n-1):0];
GBusAddr[35:0] = P2GIOGBASE[35:8] | PCIAddr[7:0];
29
1
1
1
1
1
1
1
1
1
1
Figure 16-8 Target Access Memory Window
28
0
1
1
1
1
1
1
1
1
1
27
0
0
1
1
1
1
1
1
1
1
G-Bus Space
0xF_FFFF_FFFF
0x0_0000_0000
26
0
0
0
1
1
1
1
1
1
1
16-12
25
0
0
0
0
1
1
1
1
1
1
24
0
0
0
0
0
1
1
1
1
1
23
0
0
0
0
0
0
1
1
1
1
22
PCI Memory Space
0
0
0
0
0
0
0
1
1
1
Memory Access Window
Memory Access Window
Memory Access Window
0xFF_FFFF_FFFF
0x00_FFFF_FFFF
0x00_0000_0000
21
0
0
0
0
0
0
0
0
1
1
Toshiba RISC Processor
20
0
0
0
0
0
0
0
0
0
1
29
28
27
26
25
24
23
22
21
20
n
Memory Size
512 MB
256 MB
128 MB
64 MB
32 MB
16 MB
8 MB
4 MB
2 MB
1 MB
TX4939
16
16