TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 403

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.16. Satellite Mode PCI Status Register (PCISSTATUS)
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
TYPE
TYPE
31:24
25:24
23
22:16
15
14
13
12
11
10:9
8
7:0
Bit
PS
PMEEN
DPE
SSE
RMA
RTA
STA
DT
MDPE
Mnemonic
DPE
31
15
R
0
SSE
30
14
R
0
Reserved
Power State
PME Enable
Reserved
Detected Parity
Error
Signaled System
Error
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
Set DEVSEL
Timing
Data Parity
Detected
Reserved
RMA
RESERVED
29
13
R
Field Name
0
RTA
28
12
R
0
Figure 16-27 Satellite Mode PCI Status Register
Table 16-28 Satellite Mode PCI Status Register
STA
27
11
R
0
PowerState (Default: 0x0)
This is a shadow register of the PowerState field in the PMCSR Register.
PME_En (Default: 0x0)
This is a shadow register of the PME_En bit of the PMCSR Register.
Detected Parity Error (Default: 0x0)
This is a shadow register of the PCISTATUS.DPE bit.
Signaled System Error (Default: 0x0)
This is a shadow register of the PCISTATUS.SSE bit.
Received Master Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.STA bit.
DEVSEL Timing (Fixed Value: 0x1)
This is a shadow register of the PCISTATUS.DT field.
Master Data Parity Error Detected (Default: 0x0)
This is a shadow register of the PCISTATUS.MDPE bit.
26
10
DT
R
0
25
9
16-39
PS
00
R
MDPE
24
R
8
0
PMEEN
23
R
0
7
Description
22
6
21
5
RESERVED
20
Toshiba RISC Processor
4
RESERVED
19
3
18
2
17
1
TX4939
⎯
R
R
⎯
R
R
R
R
R
R
R
⎯
R/W
16
0
16
16