TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 303

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
14.3.10. Chain DMA Transfer
Table 14-4 shows the data structure in memory that the DMA Command Descriptor has. When the Simple Chain bit
(SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial four double words are used. DMSAIRn,
DMDAIR, DMCCRn, and DMCSRn use the settings from when DMA started. In addition, all eight double words are used
when the Simple Chain bit (SMPCHN) is cleared.
Saving the start memory address of another DMA Command Descriptor in the Offset 0 Chain Address field makes it
possible to construct a chain list of DMA Command Descriptors (Figure 14-6). Set “0” in the Chain Address field of the
DMA Command Descriptor at the end of the chain list.
When DMA transfer that is specified by one DMA Command Descriptor ends, the DMA Controller automatically reads the
next DMA Command Descriptor indicated by the Chain Address Register (Chain transfer), then continues DMA transfer.
Continuous DMA transfer that uses multiple Descriptors connected into such a chain-like structure is called Chain DMA
transfer.
Since the DMA Channel Status Register is also overwritten during Chain transfer when the DMA Simple Chain bit
(SMPCHN) is cleared, be sure not to unnecessarily clear necessary bits.
Placing DMA Command Descriptors at addresses that do not span across 32-double-word boundaries in memory is
efficient since they are read by one G-Bus Burst Read operation.
Rev. 3.1 November 1, 2005
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Offset Address
+08
+10
+18
+20
+28
+30
+38
+08
+10
+18
+20
+28
+30
+38
+08
+10
+18
+20
+28
+30
+38
“A”
“B”
“C”
Chain Address
Source Address
Destination Address
Count
Source Address Increment
Destination Address Increment
Channel Control
Channel Status
Figure 14-6 DMA Command Descriptor Chain
Field Name
Table 14-4 DMA Command Descriptors
14-15
DMA Chain Address Register (DMCHARn)
DMA Source Address Register (DMSARn)
DMA Destination Address Register (DMDARn)
DMA Count Register (DMCNTRn)
DMA Source Address Increment Register (DMSAIRn)
DMA Destination Address Increment Register (DMDAIRn)
DMA Channel Control Register (DMCCRn)
DMA Channel Status Register (DMCSRn)
Transfer Destination Register
+08
+10
+18
+20
+28
+30
+38
+08
+10
+18
+20
+28
+30
+38
“D”
“E”
Toshiba RISC Processor
TX4939
14
14

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