TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 525

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
see 18.4.3.6 Reception Fragment Size Register, 18.4.3.8 Free Descriptor Area (FDA) Register, and 18.3.7.2.1 BDCtl field
(buffer descriptor control).
18.3.9.3.3. Initializing a reception descriptor area
You can initialize a reception descriptor by writing in the Free Descriptor Area Base Register or the Free Descriptor Area
Size Register. The Ethernet Controller starts writing to the reception queue in the reception descriptor area according to
these registers.
18.3.9.4. Transmitting frames
Paragraph 18.3.9.3.1 Initializing the transmission queue described transmission in a batch process. For each frame
transmission batch, the system initializes the transmission queue and sets a Transmission Frame Pointer Register at the
head of the queue.
In the case of continuous polling transmission, the frame descriptor list ends at the dummy frame descriptor owned by
the system. The Ethernet Controller enters the Polling mode when it reaches a dummy record. In this mode, the Ethernet
Controller periodically checks the frame descriptor Control (FDCtl) field and waits for the system to set the COwnsFD bit.
The Transmission Polling Counter Register controls the polling frequency.
To transmit frames in the Continuous Polling mode, the system writes the frame descriptor of the frame to be transmitted
at the end of the transmission queue. The system overwrites the old dummy frame descriptor, creates a new dummy
frame descriptor, and sets the FDNext field of the old frame descriptor in a new dummy frame descriptor. After that, it sets
the COwnsFD bit of the old frame descriptor and transfers ownership to the Ethernet Controller.
18.3.9.4.1. Signaling transmission completion
The system can fetch transmission completion information in various ways.
You can set interrupts to occur either at the end of each frame or at the end of selected frames. When polling the
Transmission Frame Pointer Register, it has an invalid value (a value set in FDNext while EOL=1) in the Batch
Processing mode or has a dummy frame descriptor address when in the Continuous Polling mode.
Rev. 3.1 November 1, 2005
Request an interrupt.
Poll the FDCtl field of the transmitted frame descriptor and confirm system ownership.
Poll the Transmission Frame Pointer Register.
18-33
Toshiba RISC Processor
TX4939
18
18

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