TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 168

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

INTC
8.3.5. Interrupt Request Detection
In order to perform interrupt detection, each register of the Interrupt Controller is initialized, and then the IDE bit of the
Interrupt Detection Enable Register (IRDEN) is set to “1.” All interrupts detected by the Interrupt Controller are masked
when this bit is cleared.
It is possible to set each interrupt factor detection mode using Interrupt Detection Mode Register 0, 1, and 2 (IRDM0,
IRDM1, and IRDM2). There are four detection modes: Low level, High level, falling edge, and rising edge.
The detected interrupt factors can be read out from the Interrupt Pending Register (IRPND) unless the IDE bit of IRDEN is
not cleared.
8.3.6. Interrupt Level Assigning
Interrupt levels from 0 to 7 are assigned to each detected interrupt using the Interrupt Level Register (IRLVL0-7). Interrupt
level 7 is the highest priority and interrupt level1 is the lowest priority. Level 0 interrupts will be masked (Table 8-2).
The priorities set by these interrupt levels will be given higher priority than the priorities provided for each interrupt source
indicated in Table 8-1.
8.3.7. Interrupt Priority Assigning
When multiple interrupt requests exist, the Interrupt Controller selects the interrupt with the highest priority according to the
priority level and interrupts number. Interrupt factors with an interrupt level lower than the interrupt level specified by the
Interrupt Mask Level Register (IRMSK) will be excluded (masked).
When the interrupt with the highest priority is selected, then the interrupt number of that interrupt is set in the interrupt factor
field (CAUSE) of the Interrupt Current Status Register (IRCS), the interrupt level is set in the Interrupt Level field (LVL), and
the Interrupt Flag bit (IF) is set.
Priorities are assigned as follows.
In addition, the interrupt priority assignments are re-evaluated under the following conditions. At this time, the interrupt with
the highest priority is selected and the Interrupt Factor field (CAUSE) and Interrupt Level field (LVL) of the Interrupt Current
Status Register (IRCS) are set again.
Rev. 3.1 November 1, 2005
When interrupt levels differ, the interrupt with the higher interrupt level has priority (Table 8-2)
When multiple interrupts with the same interrupt level are simultaneously detected, the interrupt with the smaller
When an interrupt request with a higher interrupt level than that of the currently selected interrupt is detected.
When the interrupt level (IRLVLn.ILm) of the currently selected interrupt changes to a value smaller than the
When the currently selected interrupt is cleared (refer to 8.3.10 Clearing Interrupt Requests).
interrupt number has priority.
However, when the interrupt levels are equal, the Interrupt Level field (LVL) does not change even if the interrupt
number is small.
current setting.
Priority
Mask
High
Low
Table 8-2 Interrupt Levels
8-6
Interrupt Level
(IRLVLn.ILm)
110
101
100
011
010
001
000
111
Toshiba RISC Processor
TX4939
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