TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 484

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
Following is the flow of each control signal at the transfer start position:
The following table shows the timing parameters when transfer starts.
Rev. 3.1 November 1, 2005
A
B
C
D
E
Wait for DMARQ to become active (“High”).
Set HA to “0h” and CS0N and CS1N to “1” when transfer preparations inside the controller are complete.
Wait for the specified time, then make the DMACKN active (set to “0”).
Wait for the specified time, then set DIORN and DIOWN to “0”.
Wait for IORDY to change, then send data to the controller.
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Table 17-11 Timing Parameters when Ultra DMA Transfer Starts
Mode
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
HA, CS Valid -
DMACKN “0”
17-30
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
DIORN/DIOWN “0”
DMACKN “0” -
Toshiba RISC Processor
TX4939
17
17

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