TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 720

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Electrical
28.4. AC Characteristics
28.4.1. MSTCLK, MSTCLK2 AC Characteristics
28.4.2. Power ON AC Characteristics
RESET* Width Time consists of all PLL stabilized Time and logic reset operation time.
Rev. 3.1 November 1, 2005
MSTCLK,
MSTCLK2
MSTCLK, MSTCLK2
RESET* Width Time
Master Clock Input Cycle
Master Clock Input Frequency
Master Clock High Time
Master Clock Low Time
CPUCLK Frequency
Master Clock Rise Time
Master Clock Fall Time
All PLL Powers
Note 1: TX4939 operation is only guaranteed when the power is stable, PLL secures the PLL oscillation
Note 2:
VddIN, VddIO
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
RESET*
stability time tMCP_PLL and is in the Enable state.
0.8 VddIO
0.2 VddIO
Item
Item
2
Figure 28-2 Power On Reset Timing Diagram
MSTCLK, MSTCLK2 Stabilized Time
Figure 28-1 MSTCLK Timing Diagram
f
f
t
t
t
t
MCP
MCK
MCH
MCL
MCR
MCF
T
CPU
Symbol
RESETW
Power On Reset Timing Diagram
MSTCLK, MSTCLK2 Timing Diagram
Symbol
t
MCP
T
RESETW
28-4
Condition
t
MCH
Condition
Min.
t
200
MCF
23
23
1
1
t
MCL
Typ
300
50
20
Toshiba RISC Processor
t
MCR
Min.
10
Max
400
27
27
2
2
Max.
Unit
MHz
MHz
nS
nS
nS
nS
nS
Unit
mS
TX4939
28
28