TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 340

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
15.7. Memory Access
15.7.1. Address Mapping
It is possible to map the DRAM address to an arbitrary physical address using the DDR Mapping Window registers.
When the system receives an effective physical address, (EPA), it checks following condition for enabled window(s).
Then, if it is true, Corresponding DDR channel will be accessed with following DDR_EFFECTIVE_ADDRESS.
Each window has a resolution of 1MB.
Rev. 3.1 November 1, 2005
IF ( ( EPA <= DRWINUP_ADRS ) && ( EPA >= DRWINLO_ADRS) )
DDR_EFFECTIVE_ADDRESS = EPA – DRWINLO_ADRS + DRWINOF_ADRS
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Toshiba RISC Processor
TX4939
15
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